speed, even in a fully static design. Sub-32nm FETs are horribly leaky.
ust be minimised. Hence I mentioned sticking with a larger process.
always poor, because it makes it much harder to write correct, efficient p rograms.
h I propose will be running many times more apps & background tasks than to day (a topic for another day perhaps) can at least make good use of many mo re cores/CPUs. And it can choose whichever CPUs deliver the wanted result i n the wanted time with the least energy use.
size chips, as I noted upthread.
tsink and soldering 20mm wide strips of Parlux to its connections?
FWIW what I had in mind was a handheld computer the size of a smartphone, s o it can't run hot. This at least reduces thermal expansion.
What's best is for the manufacturer to design the system based on requirements, available technology, and economics. Putting everything one chip makes the I/O impossible (the I/O has to be rerouted around failed chips). Bandwidth is only money. Latency is forever.
The 3090 TCMs I know about had either 100 of 121 chips per module. A Clark board ( a giant PCB about half an inch thick with a zillion layers) held (i irc) 9 of them. Power supplies were something like +1.6 and -3.3V at 8000 a mps. The bus bars were made of plated copper angle stock, iirc about 1-1/4 x 1-1/4 x 1/8 inch. So that's 40 kW per board, circa 1991.
CPU boards held six TCMs and channel directors, nine, IIRC. A system could have four CPUs and six channels, IIRC.
With all that power, the density isn't all that high. I once calculated the power density of the dual-core processor I worked on. It came out to something like 1E9 times the power density of the sun. ;-)
a a series of logic gates that connect or disconnect, and power rails too f or the 50mW CPUs? Maybe to guard against a bad CPU not being disconnectable due to coincident logic gate failures one can use multiple busses.
n
it
tem, followed by local neighbourhood system that tests & disconnects severa l CPUs etc. Putting all eggs in one basket is not a good plan - unless it's simple enough that the yield is high enough for that bit of silicon.
Yes. Which will be running a vast number of tasks in a handheld device. Phy sics prevents a low power THz CPU happening hence a massive number of cores /cpus is the viable option.
I expect i/o will largely be optical and/or wireless. An assortment of comp romises must be tolerated to get such a beast working, but the end result i s what I'm looking for.
Rerouted, not really. There will be several busses each connecting to many CPUs, the most suitable viable CPU will switch on to take each available ba tch of data/instructions.
ck speed, even in a fully static design. Sub-32nm FETs are horribly leaky.
e must be minimised. Hence I mentioned sticking with a larger process.
rly always poor, because it makes it much harder to write correct, efficien t programs.
hich I propose will be running many times more apps & background tasks than today (a topic for another day perhaps) can at least make good use of many more cores/CPUs. And it can choose whichever CPUs deliver the wanted resul t in the wanted time with the least energy use.
er-size chips, as I noted upthread.
heatsink and soldering 20mm wide strips of Parlux to its connections?
, so it can't run hot. This at least reduces thermal expansion.
Yes, but with a vast number of cores, vast RAM and humungous data storage a ll in 1 block of silicon. As said in the OP.
IO possibilities so far include: optical LEDs optic fibre solder data lines to Parlux partially flexible pins into sockets connection to pcb via a sheet of insulating dielectric wireless comms might also be an option I suppose even going back to a 1970s style mass of twisted pairs of flexible wires soldered on could be possible with machine assembly, albeit hateful.
via a series of logic gates that connect or disconnect, and power rails to o for the 50mW CPUs? Maybe to guard against a bad CPU not being disconnecta ble due to coincident logic gate failures one can use multiple busses.
tion
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system, followed by local neighbourhood system that tests & disconnects sev eral CPUs etc. Putting all eggs in one basket is not a good plan - unless i t's simple enough that the yield is high enough for that bit of silicon.
Physics prevents a low power THz CPU happening hence a massive number of co res/cpus is the viable option.
You don't know what I'm selling
ompromises must be tolerated to get such a beast working, but the end resul t is what I'm looking for.
ny CPUs, the most suitable viable CPU will switch on to take each available batch of data/instructions.
I don't know what you mean by 'hot driver', but all sections of the chip ar e shut down if faulty, including busses.
AFAIK there is no equivalent of this thing today, with lots of CPUs, lots o f busses and multiples of everything else. Manufacturers are more into not using redundancy, selling the perfect ones and scrapping the bad. That work s when your amount of silicon per device is small enough to avoid defects, it certainly doesn't work for whole wafer circuits, or in this case whole b lock circuits.
ses via a series of logic gates that connect or disconnect, and power rails too for the 50mW CPUs? Maybe to guard against a bad CPU not being disconne ctable due to coincident logic gate failures one can use multiple busses.
nection
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kaging
that it
a good
ct system, followed by local neighbourhood system that tests & disconnects several CPUs etc. Putting all eggs in one basket is not a good plan - unles s it's simple enough that the yield is high enough for that bit of silicon.
e. Physics prevents a low power THz CPU happening hence a massive number of cores/cpus is the viable option.
I don't doubt it.
You still don't know what I'm selling. Go on then, what am I selling?
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f compromises must be tolerated to get such a beast working, but the end re sult is what I'm looking for.
many CPUs, the most suitable viable CPU will switch on to take each availa ble batch of data/instructions.
are shut down if faulty, including busses.
Maybe you've not read the thread. That's not how it works.
s of busses and multiples of everything else. Manufacturers are more into n ot using redundancy, selling the perfect ones and scrapping the bad. That w orks when your amount of silicon per device is small enough to avoid defect s, it certainly doesn't work for whole wafer circuits, or in this case whol e block circuits.
Of course. The only present day app for lots of CPUs and huge amounts of si licon is supercomputers. They need top performance CPUs, something this pro posed approach can not deliver.
busses via a series of logic gates that connect or disconnect, and power ra ils too for the 50mW CPUs? Maybe to guard against a bad CPU not being disco nnectable due to coincident logic gate failures one can use multiple busses .
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be a good
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nnect system, followed by local neighbourhood system that tests & disconnec ts several CPUs etc. Putting all eggs in one basket is not a good plan - un less it's simple enough that the yield is high enough for that bit of silic on.
n
vice. Physics prevents a low power THz CPU happening hence a massive number of cores/cpus is the viable option.
Not even close.
ound
t of compromises must be tolerated to get such a beast working, but the end result is what I'm looking for.
to many CPUs, the most suitable viable CPU will switch on to take each ava ilable batch of data/instructions.
ne
hip are shut down if faulty, including busses.
I see you've missed a central concept of this.
lots of busses and multiples of everything else. Manufacturers are more int o not using redundancy, selling the perfect ones and scrapping the bad. Tha t works when your amount of silicon per device is small enough to avoid def ects, it certainly doesn't work for whole wafer circuits, or in this case w hole block circuits.
silicon is supercomputers. They need top performance CPUs, something this proposed approach can not deliver.
device. Physics prevents a low power THz CPU happening hence a massive num ber of cores/cpus is the viable option.
More or less, but I'm not selling it.
around
ment of compromises must be tolerated to get such a beast working, but the end result is what I'm looking for.
ing to many CPUs, the most suitable viable CPU will switch on to take each available batch of data/instructions.
One
e chip are shut down if faulty, including busses.
s, lots of busses and multiples of everything else. Manufacturers are more into not using redundancy, selling the perfect ones and scrapping the bad. That works when your amount of silicon per device is small enough to avoid defects, it certainly doesn't work for whole wafer circuits, or in this cas e whole block circuits.
of silicon is supercomputers. They need top performance CPUs, something th is proposed approach can not deliver.
Everyone else followed it ok. You've missed some of the core concepts somew here along the way.
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