Surge Current Turning On a PMPB13UP

a 5V circuit drawing some 3.7 mA when on. Observing the currents in the ci rcuit I see the load current rise smoothly from near zero to 3.7 mA. The g ate-source voltage slews monotonically from 0.3V to 5V. But the source cur rent has an peak of 48 mA during the transition! I would say this has to d o with charging the gate through the gate source capacitance, but when I sl ow the rate of rise of the gate, the size of this peak does not change, onl y the duration.

ing the Nexperia model.

You don't give any time duration for 48mA peak current.

If the data sheet is to be relied on, you have to put 26nC into the interna l capacitances of the MOSFET during switching, which would mean that the 48 mA pulse would be about 0.5usec wide, if it were square.

It won't be.

Figure 15 in the device data sheet shows that the gate voltage (Vgs) is con stant at -1.5V while the drain voltage is dropping from 5V to 0V.

There's about 8nC of charge that has to move into the gate region while thi s is going on. If you slow the rise of the gate voltage, this period ought to take longer. The fact that you don't seem to be seeing the flat bit on t he gate waveform suggests that you aren't doing quite what you think you ar e doing.

How are you measuring the 48mA. Is the circuit element involved even slight ly inductive?

n a 5V circuit drawing some 3.7 mA when on. Observing the currents in the circuit I see the load current rise smoothly from near zero to 3.7 mA. The gate-source voltage slews monotonically from 0.3V to 5V. But the source c urrent has an peak of 48 mA during the transition! I would say this has to do with charging the gate through the gate source capacitance, but when I slow the rate of rise of the gate, the size of this peak does not change, o nly the duration.

using the Nexperia model.

nal capacitances of the MOSFET during switching, which would mean that the

onstant at -1.5V while the drain voltage is dropping from 5V to 0V.

his is going on. If you slow the rise of the gate voltage, this period ough t to take longer. The fact that you don't seem to be seeing the flat bit on the gate waveform suggests that you aren't doing quite what you think you are doing.

htly inductive?

This is a simulation in LTspice. The width of the peak is a bit more than a microsecond. When I did the math it worked out to about right for the sp ec'd charge, but I expected that peak to drop and spread out as the gate vo ltage ramp was slowed. While the breath of the peak narrowed somewhat, the peak value remained. There are no inductances other than some parasitic t hat LTspice might be supplying. I know they include parasitic resistance a s a default in some cases.

I don't have this simulation up at the moment. It's not a big deal, it jus t struck me as odd that trying to "spread the peak" didn't work very well.

Sometimes I just can't figure out what LTspice is doing. I've tried to sim ulate a simple comparator as an oscillator where a divider is used to set t he compare voltage on the + pin with a positive feedback resistor. Then th e - pin has a cap and a feedback resistor as well. I'm trying to get a 4 t o 1 pulse to period ratio, but the voltages on the two input pins don't see m to make sense. The part, an LT1017, is rated down to 1.1 volts and it is being powered in the sim from 2.0 volts. When the inverting input cap is charging up, the output changes state 0.2 of a volt early making that porti on of the cycle shorter than the other. The bias currents and offset volta ges seem too small to account for this. The divider resistors are 1M each and the positive feedback is 150K while the negative feedback is 330K charg ing a 3.3 uF cap. This is an LT part so I have to assume the issue is not with the model.

on a 5V circuit drawing some 3.7 mA when on. Observing the currents in th e circuit I see the load current rise smoothly from near zero to 3.7 mA. T he gate-source voltage slews monotonically from 0.3V to 5V. But the source current has an peak of 48 mA during the transition! I would say this has to do with charging the gate through the gate source capacitance, but when I slow the rate of rise of the gate, the size of this peak does not change, only the duration.

m using the Nexperia model.

ernal capacitances of the MOSFET during switching, which would mean that th e 48mA pulse would be about 0.5usec wide, if it were square.

constant at -1.5V while the drain voltage is dropping from 5V to 0V.

this is going on. If you slow the rise of the gate voltage, this period ou ght to take longer. The fact that you don't seem to be seeing the flat bit on the gate waveform suggests that you aren't doing quite what you think yo u are doing.

ightly inductive?

n a microsecond. When I did the math it worked out to about right for the spec'd charge, but I expected that peak to drop and spread out as the gate voltage ramp was slowed. While the breath of the peak narrowed somewhat, t he peak value remained. There are no inductances other than some parasitic that LTspice might be supplying. I know they include parasitic resistance as a default in some cases.

It might be worth looking at the specific MOSFET model that LTSpice is usin g for the device. Nexperia used to be pretty good about providing Spice mod els for their devices, but a quick look at their website didn't get me anyt hing.

If you probe voltages and currents inside the model you may get a bit more insight.

ust struck me as odd that trying to "spread the peak" didn't work very well .

imulate a simple comparator as an oscillator where a divider is used to set the compare voltage on the + pin with a positive feedback resistor. Then the - pin has a cap and a feedback resistor as well. I'm trying to get a 4 to 1 pulse to period ratio, but the voltages on the two input pins don't s eem to make sense. The part, an LT1017, is rated down to 1.1 volts and it is being powered in the sim from 2.0 volts. When the inverting input cap i s charging up, the output changes state 0.2 of a volt early making that por tion of the cycle shorter than the other. The bias currents and offset vol tages seem too small to account for this. The divider resistors are 1M eac h and the positive feedback is 150K while the negative feedback is 330K cha rging a 3.3 uF cap. This is an LT part so I have to assume the issue is no t with the model.

How much parallel capacitance are you setting for each of the 1M divider re sistors? L-trimmed surface mount parts have less than spiral cut leaded res istors (which mostly came out at 0.03pF if I remember rightly).

or on a 5V circuit drawing some 3.7 mA when on. Observing the currents in the circuit I see the load current rise smoothly from near zero to 3.7 mA. The gate-source voltage slews monotonically from 0.3V to 5V. But the sour ce current has an peak of 48 mA during the transition! I would say this ha s to do with charging the gate through the gate source capacitance, but whe n I slow the rate of rise of the gate, the size of this peak does not chang e, only the duration.

am using the Nexperia model.

nternal capacitances of the MOSFET during switching, which would mean that the 48mA pulse would be about 0.5usec wide, if it were square.

is constant at -1.5V while the drain voltage is dropping from 5V to 0V.

le this is going on. If you slow the rise of the gate voltage, this period ought to take longer. The fact that you don't seem to be seeing the flat bi t on the gate waveform suggests that you aren't doing quite what you think you are doing.

slightly inductive?

han a microsecond. When I did the math it worked out to about right for th e spec'd charge, but I expected that peak to drop and spread out as the gat e voltage ramp was slowed. While the breath of the peak narrowed somewhat, the peak value remained. There are no inductances other than some parasit ic that LTspice might be supplying. I know they include parasitic resistan ce as a default in some cases.

ing for the device. Nexperia used to be pretty good about providing Spice m odels for their devices, but a quick look at their website didn't get me an ything.

e insight.

just struck me as odd that trying to "spread the peak" didn't work very we ll.

simulate a simple comparator as an oscillator where a divider is used to s et the compare voltage on the + pin with a positive feedback resistor. The n the - pin has a cap and a feedback resistor as well. I'm trying to get a 4 to 1 pulse to period ratio, but the voltages on the two input pins don't seem to make sense. The part, an LT1017, is rated down to 1.1 volts and i t is being powered in the sim from 2.0 volts. When the inverting input cap is charging up, the output changes state 0.2 of a volt early making that p ortion of the cycle shorter than the other. The bias currents and offset v oltages seem too small to account for this. The divider resistors are 1M e ach and the positive feedback is 150K while the negative feedback is 330K c harging a 3.3 uF cap. This is an LT part so I have to assume the issue is not with the model.

resistors? L-trimmed surface mount parts have less than spiral cut leaded r esistors (which mostly came out at 0.03pF if I remember rightly).

None. The oscillation rate is in the sub Hz range. When I zoom in to view what is happening at the trip point the inverting input waveform looks lik e a DC value.

There are at least four configurations of astable multivibrators. The comp arator topology moves the threshold with positive feedback while the topolo gy used in Win's LED blinker in his recent USB powered device switches the capacitor up and down and the resistor in the opposite direction providing charge and discharge from the same threshold. The cross coupled transistor circuit is a third and the 555 timer using two comparators and a FF is a f ourth.

The only one I can simulate with actual models uses transistors. That woul d take three transistors rather than a single package like NOR gates. The

Using logic gates in Win's topology would work fine for me, but I don't tru st the simulations since only ideal models are available. I always have co ncerns about oscillators starting. I've had to generate my own models for several parts and this is getting old for such a (supposedly) simple circui t. I might go with the transistor version. I can get duals and share a pa ckage with another part of the circuit.

The PMPB13UP is a 13-amp MOSFET that can handle 240W dissipation for 100us. Do you need such a serious part?

Keeping the BOM small. The current is irrelevant. The part has a low Vth and a very low on resistance and is only 2mm sq spec'd for 2W with proper h eat sinking which makes it a good choice for the current limiting circuit. Why add another part to the BOM? I'm a big fan of keeping my BOMs short. I tend to reuse resistor values and caps where possible. Fab houses never have to reload PnP machines to run more parts.

Actually, this FET may disappear depending on the oscillator circuit. Curr ently there is an alarm/ signal and a mute signal. Rather than add gates t o combine them, the alarm/ signal pulls the sounder down and something driv ing from the mute signal will pull the other end of the sounder up. It nee ds to be open emitter/source to prevent reverse driving the sounder, so unl ikely to be a chip output... hence the PFET. I suppose I could use the 2N2

To eliminate the voltage drop of the alarm signal (comparator open collecto r output) I might use the comparator low true output to provide power throu gh the PFET to the entire sounder circuit... all 3.1 mA of it. That might be more effective and simpler than what I'm doing now.

BTW, I looked at using the inverter based blinker circuit from your recent design, but the duty cycle is very hard to control with variations in Vth o f the inverters. The data sheet always talks about 20% to 80% which likely is very conservative, but I don't know what is realistic and it is easy to design a circuit that won't oscillate, at least in LTspice.

Well, in practice it isn't that bad. But it's not good either. Take a look at the updated circuit. I've left the original in place to play with it, but have reassigned LED control to the processor. It's running at 32kHz, whenever the 3.3V supply is ON. At 12uA, it can efficiently run the LED at its 0.5% operating current. OTOH, CMOS oscillators suffer from high rail-rail currents as the voltage approaches the threshold, destroying the intended 1mA at 0.5% LED duty cycle = 50uA.

Where would I find this new schematic? The old one is not even available although I have it locally.

I tried hard to not change any DropBox links;

The standalone CMOS circuit might have a 100 to 200uA drain, while the controller might have an 80uA drain.