Stabilizing regulators with low esr output caps (Ceramics and polymer)

The theory is good. You may get into trouble with the feedforward schemes, but the series resistor seems solid.

Yup. I've done even better. If you don't want the added dissipation just use a small value inductor, then use an RC LPF to provide the adequate compensation. In case of a buck you won't even notice the added inductor. In one (custom linear) case the added inductor was as low as a 5mm track.

I have to use a small resistor in the high side for current sensing for current limiting anyway. If the sensing resistor can also provide the needed zero bonus.

I tried to simulate his circuits but wasn't too successful.

I'll make a PCB of each one (LDO) using a Tant caps ESR and one using the series resistor and ceramic cap. Trying to load step test these accurately on a breadboard is an exercise in futility. You never can be sure if what your looking at is resonant ringing because of all the wires or an unstable loop.

Thanks for the input

I hate to add resistance in series with the DC load current of an LDO. If I had extra voltage to waste, I wouldn't need an LDO.

I've had pretty good results with adding a resistor in series with a low ESR capacitor in the output filter. As long as that RC is closer to the regulator than the rest of the bypass capacitance, and the total bypass capacitance is not larger than the one with the series resistor, I have not yet had problems with oscillations. But it dies take some experimentation (with pulsed load current and raw supply voltage) to demonstrate the stability.

Well yes I agree, but I'm using a FDT458P for a 1A (low duty cycle) LDO so the worst case dropout is only 0.2444V, adding a 0.1 sense resistor puts this to 0.344V. This is pretty respectable.

The input voltage can be 11V down to the dropout 6.6V (I'm using a comparator for under voltage lockout). The rms current is only about

My next order I'll probably get something like the Si3441BDV this has a lower threshold voltage, comparable Rdson and it's only 0.28 cents. The only downside is it would require about 0.75" square heatsink.

That was my original plan,but this defeats the purpose of useing either a ceramic or Polymer output capacitor.

I am using a TLV2372IDR as the EA so I should be able to desighn a compensation network around the EA. Analog Devices PMOS LDO's use miller compensation (pole splitting) to remove the dependency on the ESR zero. When I attempt this in spice I get bizzare bode plot's. Even when using alternate compensation schemes I get weird plots. I dont really trust spice for LDO simulations.

The TLV2372IDR model is pretty buggy and FETS are modeled typically for switching not transcoundouctance.Any simulations I take with a grain of salt.

So the quickest way to get a reliable regulator is by using the method in the app note.

Sure; we use that same config when an opamp drives a capacitive load. Some tuning will optimize load transient response.

Some LDOs are essentially current sources. Some, like the LM1117, are inherently low output impedances; that changes things.

But for an LDO, you can also just load it...

____________ | |-------------+---------+----------->

| | | | R | | | C | C | | | | | | | | gnd gnd ____________

and avoid the series loss.

The ideal R+C devolves to one tantalum capacitor, if you can keep it from exploding. Otherwise, a big ceramic and a few tenths of an ohm is in the ballpark.

Lots of real-life regulators may see many uF of creamic caps as loads, on other sheets of the schematic.

John

One of the problems with LDO design is the ESR of the output cap must fall within a certain range for the loop to remain stable.

Here are some comments from a post by Tim Shoppa on using ceramic caps with LDO regulators. The ESR is usually too low and can cause oscillation, and the bias voltage on Y5V dielectric can cause a significant drop in capacitance:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 09 Feb 2004 09:14:28 Tim Shoppa Selecting > 1uF ceramic caps

R. Legg:

The ESR problem with 'LDO' regulators is not one that applies specifically to ceramic capacitors, or even to LDOs; it's a problem that applies generally to all regulators with PNP or P-chanel output pass transistors, due to the added inversion in their control structure and the capacitive nature of their normal load.

Leeper:

Take a 6V 10uf Y5V, put it on a 5V rail for filtering, and you end up with an effective capacitance of 1uf.

Here are some articles showing why LDO regulators are sensitive to output cap ESR. The url's are omitted since they often change, but google will find them very quickly.

AN1148.PDF 205,195 Compensating Low-Dropout Regulators AN682.PDF 879,026 New Generation of Low Dropout Regulators AND8028.PDF 38,766 Precision Sub-One Volt 1.7 Ampere Output LDO SLVA068.PDF 68,595 LDO Fundamental Theory SLVA072.PDF 291,538 LDO Technical Review SLVA079.PDF 202,342 LDO Terms and Definitions SLVA115.PDF 85,754 Regulator ESR Stability SLYT151.PDF 468,245 Compensation Transient Response SLYT187.PDF 254,973 Understanding the Stable ESR Range SLYT194.PDF 246,355 LDO Linear Stability Analysis SR003AN.PDF 73,945 Compensation for Linear Regulators SR004AN.PDF 41,598 Linear Regulator Output Structures

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Analog Devices has found a solution to the ESR problem:

"Solving Stability Problems of Low Dropout Regulators"

and National Semiconductor solved it also:

"Capacitors are key to voltage regulator design"

So with careful design, you can make a LDO regulator immune to the ESR of the output cap.

Regards,

Mike Monett