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Sigma-Delta vs. Ramp

I need to sample a number of analog signals in an FPGA. I don't want to us e a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals.

If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs a nd the signal output. Three of my input signals need to be sampled at 1 ks ps and 12 bits, so I'm thinking this is the best way to do it. Four other signals are low speed and so one input can be multiplexed between them. I can make an adequate mux with resistors and an enable signal on the four in puts. So that is 7 I/Os for these four inputs and 9 for the higher speed s ignals (not that 1 ksps is fast, lol).

The main clock is 16 MHz and I could probably add an oscillator for somethi ng faster if I need it. I'm wondering if it is practical to save a few pin s by generating a ramp instead and using a single output for the comparator s rather than four outputs.

To get 12 bit resolution on a full scale ramp would preclude PWM. A sigma delta DAC might be able to give adequate resolution, but I'm not sure the n umbers add up.

This is a bit frustrating. Lattice has this excellent device for what I ne ed and they provide it in an easy to use package, but it's just a bit shy o n I/O count for this app. I suppose I could add I/O expander chips to driv e the LEDs. That would free up lines. It just seems like a silly thing to do. When everyone else is making smallish FPGAs with 200 I/Os and package s to match, these parts have 39 I/Os max regardless of package. The 48QFN is the large package in this family.

4 kLUTs, 10 kB of RAM, 4 DSP units and a PLL, but 39 I/Os max.

The pin count problem could be solved by using the single pin LEDs. But I don't know how much space I need to leave for the part to be out of alignme nt from soldering. The light pipe we are using has a 5x5 mm space for the LED chip. One side of that space has a leg. So the LED will have to be of f center. How far off center depends on the amount of tolerance required f or the LED to float around during soldering.

They use vision machines to check for missing components and misalignment l ike diodes being reversed. Can they check for chips not well centered? I wonder what tolerance is normally applied?

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  Rick C. 

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Reply to
Ricketty C
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use a BGA so the I/O count is rather limited as well as the variety of FPGA s. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals.

and the signal output. Three of my input signals need to be sampled at 1 ksps and 12 bits, so I'm thinking this is the best way to do it. Four othe r signals are low speed and so one input can be multiplexed between them. I can make an adequate mux with resistors and an enable signal on the four inputs. So that is 7 I/Os for these four inputs and 9 for the higher speed signals (not that 1 ksps is fast, lol).

hing faster if I need it. I'm wondering if it is practical to save a few p ins by generating a ramp instead and using a single output for the comparat ors rather than four outputs.

a delta DAC might be able to give adequate resolution, but I'm not sure the numbers add up.

need and they provide it in an easy to use package, but it's just a bit shy on I/O count for this app. I suppose I could add I/O expander chips to dr ive the LEDs. That would free up lines. It just seems like a silly thing to do. When everyone else is making smallish FPGAs with 200 I/Os and packa ges to match, these parts have 39 I/Os max regardless of package. The 48QF N is the large package in this family.

I don't know how much space I need to leave for the part to be out of align ment from soldering. The light pipe we are using has a 5x5 mm space for th e LED chip. One side of that space has a leg. So the LED will have to be off center. How far off center depends on the amount of tolerance required for the LED to float around during soldering.

like diodes being reversed. Can they check for chips not well centered? I wonder what tolerance is normally applied?

Add a 20 cent microcontroller with ADC. Then you also get 20 more IO and fl exibility

Cheers

Klaus

Reply to
Klaus Kragelund

o use a BGA so the I/O count is rather limited as well as the variety of FP GAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count top s at 39 and that has to include the JTAG/configuration signals.

ts and the signal output. Three of my input signals need to be sampled at

1 ksps and 12 bits, so I'm thinking this is the best way to do it. Four ot her signals are low speed and so one input can be multiplexed between them. I can make an adequate mux with resistors and an enable signal on the fou r inputs. So that is 7 I/Os for these four inputs and 9 for the higher spe ed signals (not that 1 ksps is fast, lol).

ething faster if I need it. I'm wondering if it is practical to save a few pins by generating a ramp instead and using a single output for the compar ators rather than four outputs.

gma delta DAC might be able to give adequate resolution, but I'm not sure t he numbers add up.

I need and they provide it in an easy to use package, but it's just a bit s hy on I/O count for this app. I suppose I could add I/O expander chips to drive the LEDs. That would free up lines. It just seems like a silly thin g to do. When everyone else is making smallish FPGAs with 200 I/Os and pac kages to match, these parts have 39 I/Os max regardless of package. The 48 QFN is the large package in this family.

t I don't know how much space I need to leave for the part to be out of ali gnment from soldering. The light pipe we are using has a 5x5 mm space for the LED chip. One side of that space has a leg. So the LED will have to b e off center. How far off center depends on the amount of tolerance requir ed for the LED to float around during soldering.

nt like diodes being reversed. Can they check for chips not well centered? I wonder what tolerance is normally applied?

flexibility

Oh, if this is the same application with the motor control, the microcontro ller can only be used for non-safety functions

Reply to
Klaus Kragelund

If this is related to the ventilator project, it should be noted that these might be used close by to a defibrillator, so make sure that your device EMC handling is adequate. This is a reason to avoid processors or sequential logic whenever possible.

Reply to
upsidedown

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