Schematic preferences

One other note: While Pulsonix is "simple-minded" and just replicates and shorts the pins of all the replicants together when you use PART[m:n] reference designators, I was intrigued to learn that some packages take this notion even further: Microwave Office will let you place, e.g., U[1:5] and draw a wire from some pin on the IC to say, two resistors drawn in parallel, R[1:2], 1k and R[3:5], 2.2k. It then slaps down 5 ICs and 5 resistors on the board, hooking up 2 of the ICs to 1k resistors and the other 3 to 2.2k resistors.

I suspect indiscrimnate use of such a feature can rapidly lead to schematics that are actually more confusing than helpful, but it was kinda interesting to see what at least some CAD tool designers are at least *thinking* about different ways to express connectivity.

---Joel

(cough) Um, I knew a number of digital designers back in the '90s who used Xilinx's schematic capture tools to define their logic. Even in the '00s people still were, although by then I think there was a sense that you were a bit of a fossil if you hadn't switched over to VHDL, Verilog, or similar.

My 15 year old printer already does 600dpi!

Inkjet is crap indeed. Although the colors have some added value.

I always print diagrams. First to place the PCB secondly to probe the prototype. I always draw components like their actual footprint. That makes it much easier to find the proper pin.

My Canon PIXMA iP6000D prints at fair quality. The main problem is regular paper wicks a little bit, so you get "hairy" pixels. If you want photo quality, print on photo paper -- does an excellent job.

It also depends how you print. "Normal" quality doesn't look too good (it prints in color with typical resolution, but it doesn't seem to pay particular attention), while "high" quality looks okay, at the expense of going quite slow. It also does duplex printing automatically (it has a page flip roller), but it takes an extremely long time (it just sits there -- the driver claims "Drying Paper").

Tim

It still takes time. Management usually has other things to do with my time. ;-)

So? It's not rocket-surgery. OrCrap comes close but botches the net names completely. VHDL/Verilog is all hierarchical and it seems to work pretty well. Even the graphics tools drill into the hierarchy fine.

Power supplies are globals.

Not buying it.

Ever see a processor design? It is *exactly* the same thing.

Which file documents the instruction that gets executed in a VHDL design? ;-)

Just name the main file ProjectName_Main.c or Project_Start.c. It is

I use both paper and the screen together. Each has its strengths. I have to support manufacturing, too.

I just lost about half my desk space. We moved downstairs to bigger digs so we have more wasted space and less office space. Well, the other engineer and the lead firmware guy ended up with a huge offices. I'm not "supposed" to use my office as a lab anymore. :-(

Double ick. I'd throw that schematic away without reading. :-)

Yes!

If they're individual GPIOs leave them separate because they are. If it's a bus, draw it as a bus, because it is. It's not a difficult concept to draw things as they're used.

I don't generally put 100 pins on a device. FPGAs and processors get homogeneous symbols spread where they make sense. The address/data bus may end up on the memory page. Power on the decoupling page (often with more than one large component).

It's not necessarily more. It's simpler.

I don't think we have a board with more than one RAM or Flash. In particular, memory should be crammed together with busses. These sheets rarely have problems that need troubleshooting. When they do it's easier to have everything on one sheet; the whole bloomin' bus.

They never get "published", but no, I often print segments in B&W. All the information is still there, just not as obvious without color queues.

Silly analogy. This stuff is *not* safety critical, nor is any critical information lost without color.

Our "client" isn't about to get *any* schematics. ;-)

It was the only way a large system could be managed. Laser printers soon replaced the chain printers but they were still character based. Of course everyone else was still hand drafting stuff when we were auto-routing. As a lifeline to Intel, they got the system (and had put a usable front end on it so their engineers would use it ;).

I didn't say one had to be stupid. Some here are advocating that too.

Seven lines up: "So, I will often label signals ignoring any "negated" convention."

That is a positive active signal, so has no "_n".

Again, a positive signal. That's exactly how you match signal name polarity with component "dot" polarity and DeMorgan correct symbols. You *are* using proper polarity conventions; they're all positive active.

I do it the other way around. I want control over the product, as much as possible. I'll often move connectors around so they make more sense and I want my schematics to resemble reality.

It *is* targeting the lowest common denominator. Dumbing everything down because some are dumb, i.e. typical leftist.

Sounds like Augat. Loved their stuff.

He couldn't count either? I was assigned a dumb technician once too. It was the last time he worked for me.

So they got rid of all color codes? The green wire in your world isn't ground? Get real.

Sure, but I still draw a table with the decode table so it's clear which address range activates each enable.

Ooooh, I don't like parts that aren't drawn.

In the '70s they used schematics. In the '80s, flow charts (VHDL wasn't ready for prime time, though some used it), and late '90s and '00s VHDL. I moved from schematics to VHDL in '98 or '99.

Ick! You must have small schematics.

HP DesignJets are pretty good. Well, ours was until IT "fixed" it.

Exactly! Read my original comment:

"E.g., RUN and STOP instead of RUN and RUNN (or NRUN)."

Obviously, this refers to *two* signals. One of those is the complement of the other (RUN -> RUNn, RUN -> STOP). The point I was making is that I will *avoid* the "_n" in favor of choosing a signal name that inherently implies the negation of its counterpart. YES -> NO. RUN -> STOP. LEFT -> RIGHT.

This avoids the "negation" issue for the most part (i.e., always name "negative" signals with their antonyms)

He assumed the socket he had installed -- since it *looked* the same (color) as the previous one he had installed -- was the same size as that previous one.

We aren't all lucky enough to have final say over who gets hired at the places we work (or, at the clients we work *for*).

In general I agree with you, but I'm OK for something as "well-known" as some dozens of bypass caps.

Again, your original comment was: "So, I will often label signals ignoring any "negated" convention." ...which is not what you're doing. Negative active signals *MUST* have a negative notation.

No it doesn't avoid negation. Parts still have negative inputs and the signal names should match. Negated names for negative logic.

Any idiot can tell the difference between a 14-pin socket and a 16-pin socket by inspection. Color isn't even involved. Nope. Not buying it.

I (eventually) get to say who works for me. They want the work done give me competence or at least someone smart enough to learn.

I wouldn't even go there. Too many ways for things to go wrong.

D Yuniskis schrieb:

Hallo,

in Germany we have well defined paper formats, all these have the same aspect ratio and the next larger format has exactly the double area of the smaller one. Perfect for reduction and magnification.

Bye

Unfortunately, not that simple on this side of the pond. The aspect ratio alternates with each successive paper size. E.g., 8.5x11 -> 11x17 -> 17x22 (same aspect as 8.5x11) -> 22x34 (same aspect as 11x17).

Sometimes, it can be a win as you can deliberately chose a size and orientation that will scale to fit something nicely (e.g., B scaled to fit on an A gives you a nice margin). But, it is something that every designer stumbles over sooner or later when they get tired of large paper formats.

Think of it as just like a hierachical block ("all your bypass caps are belong to us") -- you just can't "push" into it explicitly. :-)

--- I don't understand what you're saying, but what works for me is to name the signal appropriately and then to assign it the polarity which results in the desired action being asserted.

For example: (View in Courier)

If have a signal which goes high and I want to use that signal to trigger an RS latch which will, say, start a motor, then I'll call the signal START and I'll wire it into a pair of positive true NORs like this:

START>----A _ NOR Y--+ +--B | | | | _ A +-----Y NOR B

Let's also say that the signal required by the controller, which will turn the motor on, is a momentary low-going signal. Then the signal chain would look like this:

CONTROLLER +--------------+ START>----A _ _____ |_____ ___| NOR Y--+-->START>---O|START ON/OFF|--[MOTOR] +--B | | | | | | | | _ A +-----Y NOR B

CONTROLLER +--------------+ START>----A _ _____ |__ ___| OR Y-----+-->START>---O|ST ON/OFF|--[MOTOR] +--B U1 | | | | | ____ |__ ____| +-----------|-->STOP-----O|SP STOP|O--+ | | | | | | _ A--+ _ +--------------+ | +-----Y OR A----------------------------+ U2 B---Y _ OR U3 B--+ ____ | STOP>---------------------+

Notice that all of the gates are functionally ORs but, because of the annotation being applied to indicate function, in the real world U1 and U2 would be something like HC02 NORs, and U3 (being its De Morgan equivalent)something like an HC00 NAND.

JF

_____ Except that START and START are not complementary. In this case _____ _______ _____________ START should be something like RUNNING or START_LATCHED or some such.

YES! Thank you!