Schematic preferences

Visio does this, but I've never met an actual schematic capture program that does. I'm not sure I'd want to use such a feature personally, but it would be a nice option, certainly.

You rarely have to sit down in the lab, in front of a scope and debug the design. ;-)

One nice thing Pulsonix lets you do is to "multiply-instance" a component... you can name, e.g., a mounting hole MH[1:6] and connect it to ground, and on the layout -- poof! -- you get six grounded mounting holes.

ORCAD of course doesn't do this, having almost zero significant new development performed in something like a decade now.

If I thought that would be useful, in PSpice Schematics I'd simply create a part.

But I prefer to avoid the problem.

But I will admit to recently creating parts that overlay, allowing a representation of ESD structures associated with a PAD, AND netlisting properly. But this is not for amateurs... you need to understand the power of netlists for data transfers. ...Jim Thompson

But I have. On complex chips like the first Garmin GPS chip, I sat there in Burlington with the IBM test guys correlating test data to the test plan, and creating a final probe test procedure.

Rare now-a-days, everything always comes up working ;-)

...Jim Thompson

Visio also allows you to leave a break for crossings; much nicer than speed bumps. Both speed bumps and gaps are programmable.

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No connection Connection

How do you define "MH" and it's connections?

Certainly they have. They've developed a *lot* of new crashes.

e 3

Yes, after the schematic is all done, it is converted to a DWG for the production folks. The conversion process sometime does stuff like changing the font size. I try to keep my text well spaced out.

I don't mind the 2K7 notation so much as using a 2.7K 5% in a place where the design really needed a 1% part. I have seen cases where the design only worked because most of the 5% resistors fall inside the 2% range. If they all happen to land jelly side down, the circuit fails.

Way back when TR was the ref for a transistor on a lot of schematics. It wasn't standardized. There was also a symbol that looked like this:

--- ! ! ! ! ------!>! !----- ! ! ! ! --- ! !

That is a PNP transistor

I often have to support things in remote sites. The schematic is in the manual and may be some what degraded.

I always draw a vertical gap. I think it looks better than a solid cross, but not as hollow as a horizontal gap, which seems like there's more missing.

Tim

We drew them longer and skinnier,

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If your publisher is that bad, find a real professional.

You're still not probing the circuits so don't need all of the information contained in the schematic. The logic guys haven't even used schematics for thirty years. Before VHDL they used flow charts.

Even when it works we have to prove it. It's not like chips where we throw it over the wall to the test guys and forget it (until they come back with failing patterns our simulation didn't catch ;-).

I prepare the documents mostly for myself. I may have to revisit a design years later. I don't want to have to waste the time

The problem is, you (I) want a block diagram that gives folks a general feel for what is where in the design. But, hierarchical tools have to account for *everything*.

So, if you have tucked a voltage regulator on a sheet in "Block A" that is also used in "Block C", the block diagram wants to show that signal connecting the too. Even though it isn't significant enough to elevate to the level of prominence that you would typically embody in a block diagram.

I.e., block diagrams should deliberately hide details. Yet, this "niggling detail" gains a place of prominence on a par with major signal flow, etc.

Different scale entirely. Imagine hundreds (thousands?) of files of code. Probably hundreds of lines of code in each. With descriptive names on the files -- at least in terms of the guys who named them! :>

CPU comes out of reset. Which file documents the first instruction that it will execute? (assuming I can figure out which *other* files it will eventually wander into or through)

I try to work off the screen as much as possible. Printed copies while I am creating the schematic. And, as part of the deliverables. Most of my time spent with a design is consulting it while writing software (to make it do its thing). My designs themselves tend to work "out of the box" (unless a defective part gets stuffed, etc.) so I don't need to spend much time fretting over the hardware itself.

I just don't have much desktop space free for paper, binders, etc. Too much equipment in too little space :> And I'd rather have the equipment than space for paper! ;-)

Using small pages limits the number of signals that can be on a page. E.g., I just drew a page with an SoC which, by its very nature, has *lots* of things that will want to head off to other pages (peripherals, etc.). So, there are ~80 signals that leave the page bound for "parts unknown" :>

Quite common for SoC designs! E.g., this chip has 6 or 8 ports on it. Should I bundle each 8 bit port into a little "bus"? In which case, I doubt all 8 signals in *any* of those busses will end up on the same *page* -- let alone the same *chip*!

Too late. :>

The only time I end up with a single component per sheet is for things like SoC's. It's just too hard to get devices with 100+ pins to *fit* on a small (B) size sheet with much of anything else (besides a handful of discretes)

Cramming more onto a single page doesn't make things any easier for me to read.

Who said *one* ROM or *one* RAM? Note they each have s's on them!

Do your drawings *always* get rendered in color? Are they

There are industries in which I work where this is actually part of their "best practices". Because they acknowledge that there is a huge portion of the population that has some sort of color impairment in the vision. Likewise, restrictions on what frequencies to use in audible annunciators (e.g., if the "Evacuate the building" signal is at 20KHz, you're pretty sure most of the elderly employees aren't going to make it out! :> )

I can either adopt two different standards for work done in those industries vs. work done elsewhere; or, adopt a standard that works well in *both* places. (I've never had a client ask for a *color* version of a schematic from me :> )

Yes, I've worked out of "books" of such schematics. I wonder if anyone has ever *studied* the practice to be able to quantify how *unproductive* it is?

This ignores a huge class of components! E.g., I was just looking at a PoE controller. Drawn by the manufacturer as a "box". With pins on all four sides AS IF it was the actual chip itself! (i.e., pins were numbered sequentially around the "box"). Told me absolutely nothing about what was going on in the circuit. And, I'd wager it would be just as hard for the chip's *designer* to sort out the behavior in that circuit!

I worked with a system that restricted names to 8 characters. (or, maybe it was 6?). So, I have to keep my signal names at

How is my choice of name *not* indicating polarity? RUN indicates that the system is RUNning when it is HIGH. When the STOP signal is high (RUN_n in your parlance), then the system is STOPped.

I do a design. Later, someone decides how to make it real.

I don't see anything "leftist" about it! Rather, I don't want people screwing up my work.

I had a technician prototype a design of mine some 30 years ago (when we still used to wirewrap things). I pulled the wirewrap sockets from stock and set them on his desk in a bag. Sockets were color coded (Augat, IIRC): red and green for

I came back an hour later to see how he was doing and found him patiently *unwrapping* his work. I assumed he had just made a mistake on *that* wrap and kidded him about it: "Wrong pin?" He replied "Wrong socket." I assumed he meant he had wrapped pin X on socket Y and it should have been pin X on socket Z. No. He couldn't differentiate red from green and had used the WRONG SOCKET for that device.

I've similarly found problems where technicians got wire colors wrong in harnesses. This can be really annoying if you're talking about *big* harnesses!

That's part of the signal name. ROM_Enable, RAM_Enable, ADC_Enable, etc.

Do you do cowboys and tombstones?

;-)

-- "Electricity is of two kinds, positive and negative. The difference is, I presume, that one comes a little more expensive, but is more durable; the other is a cheaper thing, but the moths get into it." (Stephen Leacock)

Don't know for the cowboys, but aren't tombstones a production thing :-?

The degrading happens after it is published.

I recall one doodle of a guy on a skis schussing down a Miller ramp.

John