Unfortunately it hardly ever is. Mostly the time constant is 10x to 100x the sample gate width. So one either has to live just with the small delta-V as a sampled signal for processing or let this run over a hundred cycles or so and accumulate in a post sampler. Or use the feedback trick from the old HP days that John described to make the sampler cap ratchet up.
The ratcheting should be easier with the dual-gate circuit though because there won't be any leakage. Might not even need the feedback or post-sampling at all. But capacitances are probably quite high, or at least higher than 0.25pF.
Possibly the nonlinearityy could be servoed out by running a 2nd dual-gate in a slower fashion. That's how I sometimes did controllable delay circuits. It would be nice to have a dual-dual-gate FET for that but having them close to each other with some serious copper on the inner layers could work.