We have a pc board with a topside copper pour that's 2" x 1", and we cut a narrow slit to separate it into two 1" square regions.
We want to bridge the gap with conventional-construction surface-mount resistors, with the goal of getting the maximum safe power dissipation and the minimum resistance error from self-heating. In this particular case, we need precision resistance up to a watt or so, and we need to survive an overload of a few watts without longterm effects. There will be some modest air flow.
Assume the copper is thick enough to be a good heat conductor in this context.
Allowing for, say, a 20 mil gap between resistors, we could place maybe seven 2412 resistors in parallel across the gap. Or 10 or 11
1206's. Maybe 18 or so 0603's.
The revelations are that...
Using seven 0603's or seven 1206's works about as well as using seven of the 2412's. One line of reasoning suggests the 0603's might be the best choice.
Using 18 of the 0603's is a lot better than the seven 2412's.
The argument doesn't even take into account the fact that I can easily get super-low TC thinfilms in the smaller sizes, but not in 2412.
Have you considered staggering the resistors? I.e. one mostly on the left pad, next mostly on the right, next mostly on the left, etc. That way there's more airflow beside each resistor, and less heating from neigbors.
Did you take into account the current density inside the resistors themselves? Wider resistors have less density, so less heat per sq mil to dissipate. What lines of reasoning did you use?
I am left wondering why you would place all the resistors as close together as possible and then spread the heat with copper. Why not spread the resistors out over the two square inches, especially crowding them to the edges and especially the corners? This makes the copper a lot less important.
copper is doing most of the dissipation anyway. A crenellated (inter-digitated) gap would make for a more uniform heat distribution over the whole 2" by 1" (50.8mm by 25.4mm) copper pour and presumably a higher total heat dissipation for a given peak resistor temperature, so I agree with your proposition, though I'm dubious about your arguement.
The reasoning would presumably be much the same as that that led John Larkin to prefer lots of small resistors to a few large resistors in the first place - the more nearly the temperature of the copper approximates to a uniform high value, the more heat you get rid of.
I disagree. The copper is a link in the chain of conduction and convection that finally dissipates the heat into the environment, at large. If the heat source is essentially as large as the copper surface, the copper does very little under that heat source. It doesn't even hold much stored heat, compared to a fiberglass board that is much thicker, to handle heat surges.
If you can spread the individual heat sources over the entire copper surface, so that its temperature is completely uniform, then there is no reason to have the copper in the first place. The copper is just a means to spread concentrated heat over a surface, to emulate a distributed heat source, to pass that heat into the surrounding atmosphere.
Assuming DC current flow, as you add more smaller resisters, you split the resistor's center hot spots with more cooling between resistors. You may keep the area constant but the circumference increases for better cooling as you split the resistors into smaller sections. Spread out thy hot spots. It would also help, if multi layer PCB, to add a thermal spreader on the first inner layer. Revelation, I believe my 10V to 30V/-5V power supply topology was much better than yours in a previous thread! Harry
So, first one is surface area to volume ratio. Smaller things are better at dissapating heat than larger ones.
Second one is distance to copper. Shorter resistors have a shorter path for internal heat to get to the copper.
Third one is orientation. Wether vertical or horizontal the smaller, spaced, resistors will always present a greater area for convection.
Fourth one, which is tied up with all the others, will be the aspect ratio of the resistors. The smaller ones will have a relatively chunkier sort of thing compared to the bigger ones.
I presume you intended a flyback config. Since I want a solid, low-ripple -5, I'd either have to close a feedback loop on the -5, or run the boost thing open-loop somehow but generate -7 or whatever and linear-regulate that.
The open-loop thing bothers me for a couple of reasons, but there are tiny single-chip flyback things that accept feedback, so generating a pretty stiff -5 would work, and the + boost voltage can pretty much fall where it wants and still be usable... anything over maybe 25 volts on the pin diode has diminishing returns.
I would have to eval the ISDN transformer as a flyback. I suspect it won't take many volt-seconds to saturate it.
So, one of the flyback regulator chippies, an r-c to set its timing, a couple of r's for the feedback, likely an r-c for loop compensation. Space-wise it's about a wash against my three tiny chips and one r-c, but has the advantage of needing only two rectifier diodes.
So, not "much better" but pretty close overall and not a bad idea.
Hmmm, how about a single secondary with a waveform that swings -5 and
+30 or something like that, driving a BAV99 dual diode to -5 and +30 dc out? Sort of a forward+flyback dual supply all in one place. I'm not sure how to control that with just a few parts, but the secondary side sure is simple.
Mine was a simple boost from +10V input to +30V output. Two parallel windings (N=2) of your inductor, a N-FET , diode and cap. The other two parallel windings (N=1) would swing +15V and -5V. A diode and cap would catch the -5V. 6 parts total plus drive. If the +10V input is stiff and the loads do not change, a feedback loop may not be necessary. Feed back the -5V output for best results. Maybe put a LDO on the -5V output. I don't get your V*S argument. In the above topology place the windings in series for 2x*V*S. You switching frequency will determine your V*S requirements. The max voltage across any winding is 20V and to generate 30V out this topology has the lowest V*S. Ok, maybe it worth just a shot of tequila! Harry
"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...
Why don't you push pull drive a CT primary, with the CT grounded and 2 PMOS? This give you the neg 10V for free. Then the 2 series 1:2 secondaries give you 40V or so. No need for feedback.
OK, there's the pb of driving PMOS hanged on the 10V rail. Just use a LTC6900+74xx74 hanged on the same rail with their ground "floating" 5V below.
John Larkn talks about 18 0603 resistors. According to the Panasonic data sheet,
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such resistors have an area of 1.6mm x 0.8mm or 1.28mm^2. Eighteen of them get up to 23.04mm^2. The copper area is 50.8mm by 25.4mm or
1290mm^2, some 56 times larger.
Panasonic doesn't say anything about associated copper areas
Texas Instruments - working with a rather different surface mount part
- does. See page 7.
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By the look of it, the relatively high thermal conductivity of the thin copper layer on a printed circuit board is useful up to some 20mm away from the dissipating device.
True, but not applicable here - the space available to be filled with copper is a lot bigger than John Larkin seems to be prepared to fill with resistors.
Agreed. Evena thin layer of copper seems to spread the heat a lot better than the much thicker layer of glass-fibre bonded with FR4 epoxy resin underneath it, The thermal conductivity of copper is 385 W/m/K, and the conductivity of the board looks as if it will be closer to 1 W/m/K.
Just spreading those 18 or so resistors out over the 2 square inches would be a big improvement in their heating each other than having them shoulder to shoulder in a straight line.
Don't stop there. Keep in mind that when they are side by side, there is effectively a strip (as wide as the pitch of the parts) of copper in two directions leaving each resistor, not a square inch around each one. When they are spread out, you have a 1/16 inch thick by about .2 inch radius of fiber glass board under each resistor that is not much heated by anything else. And there is still almost as much total copper as there is in the single row case, by the time you connect them all in parallel or series (or series parallel).
Yes, other geometries are interesting. The limit on the number of resistors is of course cost; these thinfilms cost about 30 cents each in quantity, and copper is free. Paving the entire 2 square inches of available board area with thinfilms would be too expensive, and a sparse array doesn't heatsink the resistors much, since FR4 is such a rotten heat conductor. So we go for a large ratio of copper area to resistor area, and the copper does basically all the cooling.
The immediate problem is to use 2 sq in of board area to optimally create a high-precision, high-power resistor at reasonable cost. There are no real limits on "precision" or "power" (the product just gets better) but 150 ppm self-heating error at 1 watt is pretty good, and survival without longterm effects should be at least 3 watts. Wirewounds and TO-220 resistors would both be a pain, so we're trying to stick to available surface-mount parts.
One square of 1 oz copper has a thermal sheet resistance of about 70 K/W. Coincidentally, the sheet resistance of the typical surfmount alumina resistor substrate is about the same. We can't afford AlN thinfilms!
If you thermally ground both end-caps of a resistor, the self-heat hot-spot is obviously in the middle. The temperature rise factor, in K/W at the hot spot, depends on resistor aspect ratio, not size, and is about same for 2010, 1206, and 0603, maybe even better for the smaller sizes because of relative end-cap geometry. This alone pushes one to a larger number of small resistors, since each resistor then gets a smaller share of the available watts, so hot-spot temperature rise goes as 1/N where N is the number of resistors.
The resistor's thermal profile from self-heating (again, end-cap cooled) is roughly gaussian, peaking at the center.
For a given N, if the copper is thick, namely isothermal, the copper topology doesn't matter. All that matters is that a certain copper area is available, and that each end of each resistor gets to use the same effective copper area. But the thermal resistance of the copper is non-trivial, so something like Tony's geometry is probably better than the two 1-in square blocks, even with the same N.
There are lots of secondary effects, including ...
The solder and copper on/under the end-caps reduces effective aspect ratio
The solder on the pads helps spread heat and reduce thermal crowding.
There is some thermal conduction from the bottomside of the resistor to the board, some of that to copper. Unless you glue the resistors down, there's typically about an 8 mil air gap, which doesn't conduct much heat.
Heat can be conducted through FR4 to power/ground planes, and vias can conduct heat to pours on other layers, which can then also help dump heat into planes. On a six-layer board, theta between layers is something like 10 K/w per square inch, not trivial.
You'd need about $100K of software and another $100K of time to model this accurately. Experiments using a thermal imager would be a big help here, so we're considering one.
It is an interesting problem, and one that I've looked at in other contexts. It is most unlikely that you'd need an accurate model to make sensible design decisions.
My approach has always been to work out roughly where the heat is going and the thermal resistances on the various paths, using a hand calculator and my trusty (if dated) science data book, backed up these days by the occasional web search.
My guess it would take me a couple hours to put together a rough picture of the temperature distribution across such a board - which, at my excessively low consulting rates, wouldn't cost more than a few hundred dollars.
I haven't done it here - I'd want to know more about the intended application before committing the time - and I wouldn't all that confident about the resullts, largely because I don't really trsut any theoretical model farther than I can test it, but if such a model were backed up by an thermal imaging camera it could be quite a useful tool.
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