Redundant clock switching

What about a small FPGA? They have dedicated blocks for this purpose (google "fpga clock mux").

If it's a mission critical application, using two technologically different sources might be a good idea.

You don't; the loop filter of the PLL keeps the output frequency nearly-constant during a transition, by limiting the control voltage slew. There's actually three oscillators, one (the PLL) that tracks either the main or the backup.

Noise sensitivity of a counter-type phase detector is not good (a few extra transitions of the XOR will have only random influence on the lock). Yes, it's a dirty solution.

You are basically locking to the master, so there will be no change if the slave fails.

If the master fails, the slave could be 180 degrees out of phase. The XOR could slip lock during recovery and pop to a non-integer frequency ratio. There is no way to detect that with the XOR.

I realize that.

You are summing the outputs of two oscillators. They will drift in frequency. They will sometimes be in phase and sometimes out of phase.

You cannot maintain a useful lock under that condition unless you make the amplitude of the standby very low. Then, if the master fails, the SNR of the standby will be very poor.

This method does nothing to detect if the master or slave are oscillating at the wrong frequency.

The XOR phase detector can lock to non-integer ratios of the input frequency. This can happen while you are transitioning from one oscillator to the other. Once this happens, it is impossible to get it to lock on the correct frequency. There is no way to detect the correct locked condition.

No, that's not the idea at all: the 'standby' is a small square-wave superimposed on a larger 'main reference' square-wave, and you AC-amplify this with a saturating amplifier. So, the small signal never has a chance to reach the threshold of switching when the larger signal is present. Only when the main signal goes high/goes low/floats does the secondary signal determine any edge presented to the phase detector.

It's an analog signsl presented to the AC amplifier, but the AC amplifier output is saturated when the biggest step UP or DOWN occurs, and it's insensitive to the smaller signal entirely (unless the step slew rate is slow) because of saturation.

It's true that the XOR doesn't lock quickly; it has good gain, though, and once locked is accurate.

Maybe that's true if the oscillators aren't very near the same frequency, but I'm assuming they are. That's why they're references. There will be a lock condition at 1:1, and phase will drift up toward that lock, or will drift down toward that lock, or... when there's no drift, it's already locked.

If the XOR is too uncertain, there are other phase detectors that could be used, but I wanted the gate's gain during the transition.

The standby oscillator presents a noise signal to the main oscillator. This will cause jitter in the zero crossings to the slave pll. If you were a time-nut or interested in the Picosecond Pulse Labs publications, you would see this is an obvious source of problems.

The problem is when the master fails. The slave may be 180 degrees out of phase. The transer curve of a XOR is triangular. If the loop suddenly finds itself 180 degees out of phase, it will push the loop away from lock. Under this condition, it can find a lock point that has a non-integer ratio to the desired frequency.

If you want to guarantee lock, use a PFD.

Not really. The XOR drifts with temperature, supply voltage, op amp offsets, aging, and other factors. The PFD is locked to single edges and is sensitive only to differential drift in the dual-d phase detector.

That assumption is wrong. I have been working with XOR and PFD since 1969, and I can assure you the XOR can lock to the wrong frequency very easily and without expectation. It is a very bad phase detector.

The XOR has very poor gain compared to a PFD. The transfer curve is triangular. The transfer curve for a PFD is a vertical line.

Got to run. My timer for the laundry just went off. I have no time to review for spelling or typos or syntax problems.

You need an analogue phase detector to get good results with this trick.

Cheers

Phil Hobbs

You make the slave oscillator's tuning range too narrow for harmonic locking to occur, and make the loop filter simple enough that false-lock can't occur either. Analogue phase detectors won't lock in the wrong place then. 'Tain't rocket science--have a squint at Gardner's "Phaselock Techniques" and all will become clear.

Cheers

Phil Hobbs

For picosecond accuracy or very low phase noise, a well-done XOR is usually the best phase detector. PFDs always have some sort of deadband or anti-deadband (gain change) problem, and metastability hazards.

A single d-flop is an interesting infinite-gain phase detector with no deadband.

Sometimes with a deadband or hysteresis.

I goofed here. The transfer curve of the PFD is a sawtooth, but the lock point is in the middle of the ramp, not at the edge.

I'm not talking about harmonic locking. I'm talking about a non-integer ratio close to the correct frequency. Once it is locked there, it is impossible to pull it back to the correct frequency.

I don't know what you mean by making the loop filter simple enough that non-integer locking can't occur. The filter has to be good enough to minimize the huge ripple that occurs with the XOR.

The XOR also gives no indication it is on the wrong frequency. The PFD is guaranteed to lock on the correct frequency.

I have Gardner, 1979 and 2005 editions. Chapter 14 discusses Anomalous Locking. The closest I can find to this condition is 14.1 Sidelock, but it is not exactly what I am talking about. Gardner recommends using a FLL to get the loop close to the correct frequency, but warns it may also give false locks. I would simply use a PFD.

The XOR is the worst loop for picosecond accuracy. It drifts with just about everything. It is also the worst loop for low phase noise due to the huge ripple output. It is never used in a precision, low noise PLL.

The deadband in a PFD is easily corrected. It is caused by a slow turnon or turnof of either the + or - output. This occurs not in the PFD itself, but in the following error amplifier. It is most noticeable in the Original circuit by JT, where one side is a transistor that is in saturation and slow to turn off. A simple Baker clamp would have solved the problem.

In the event you have this problem, just add enough delay in the feedback path to ensure the + and - outputs turn on and off completely.

There is no possibility of metastability in the dual-D PFD. When the incoming pulse arrives, the D flop has no set or reset pulse applied. They are long gone.

I goofed. The PFD transfer curve is sawtooth, as is well known. But the lock point is in the middle of the ramp, not the vertical line at the edge.

But I do it. Differential input/output ECL gates and diffamp-input loop filters are stable to below 1 ps. Single-ended CMOS will always be drifty.

We are using a fast CML flop now as a bang-bang phase detector with below 20 fs jitter floor. Our test rig probably makes more jitter than the flop itself.

Oscillator injection locking was being done in the 30s, and probably earlier.

NT

The math of injection locking is complicated, though, and it's hard to be sure that a transient at the wrong time won't make the clock glitch. PLLs are more predictable that way.

Cheers

Phil Hobbs

You're describing false lock. YCLIU in Gardner if you look harder. The issue is that the pull-in signal for an XOR or analogue PD is weak, especially for narrow loops with wide tuning ranges, because it relies on beat frequency ripple going through the loop filter. What goes on is that if the loop filter's phase shift is too large at some accessible offset frequency, the pull-in signal goes to zero and the loop never locks.

But there's no reason to rely on pull-in.

I usually use an acquisition aid that basically turns the loop filter into a sweep oscillator when the loop unlocks. (It works automatically, because the loop gain drops to zero when it's unlocked, letting the much weaker positive feedback take over and make it sweep.)

PFDs have other problems, especially in low-SNR applications, which is where PLLs are most useful. They're also much noisier than DBM- or MUX-based PDs. I use PFDs occasionally, but never in a high-performance application.

Cheers

Phil Hobbs

A 74HC86 is single-ended. It will drift as I stated.

A differential dual-d is better. Less drift, much less ripple (theoretically zero), guaranteed frequency lock.

You are fooling yourself and everyone else. There is no way you can claim the NB7V52M has a 20fs noise floor. The Motorola datasheet specifies 200fs rms jitter typical, 800fs max:

The schematic you presented to the SI-LIST shows two fast comparators generating the clock and data signals. The comparators are probably the ADCMP580 series. The typical rms jitter is specified at 200ps.

So you have three 200fs parts in a string. The result is sqrt(200^2 + 200^2

• 200^2) = 346.4fs.

There is no way you can get 20fs except by some unusual averaging tricks. Even then, the rms jitter determines the performance, not the result of averaging.

This is the same kind of fraud you see in many specs. The resolution is given as XX, but the rms value may be 10 or 50 times as high. Why claim fs resolution, when the result of a measurement may be many tens of ps off.

HP used to blank unusable digits in their counters and only present valid, usable measurements. I guess that practise has stopped in the industry.

I don't see how you can claim a PFD is noisier than an XOR. Both have a linear slope through zero. The XOR has twice the slope of the PFD. The XOR has a triangular transfer curve, which means error samples beyond half the window will give the wrong polarity of feedback. The pfd has a sawtooth transfer curve, and will accept error samples up to the edge of the window and still give correct polarity feedback.

If you are working with noisy signals, you can use a very narrow loop filter with the pfd. With the XOR, you are screwed. It will pop itself out of lock.

Huh? You can get the same propogation delay from both the inputs of that gate, so the loop stabilizes at the same phase despite any thermal drift. Heck, there's two correction pulses every cycle, the phase lock doesn't drift any more than the (temperature?) change in half a 24-millionth-of-a-second, before it's corrected.

Slew isn't good for picoseconds, but for a 24 Mhz clock it's generally OK to getr a nanosecond.

The XOR's transfer curve is a triangle whose slopes are +-VDD/pi. A PFD's transfer curve is a sawtooth with slope VDD/2pi on one slope (half that of the XOR), and something much larger on the other side (the retrace).

The gain isn't infinite on the retrace, but it's generally hundreds of times larger and always poorly controlled. As you say, some PFDs such as the 4046 have a deadband right at the 0-degree point. (We've talked about that N times in this very boutique, of course.) A loop that tries to servo on that deadband will have horrible phase noise unless you use a resistor to pull it slightly to one side or another. 1M to ground is my usual recipe. The Motorola style PFDs with two outputs don't show the deadband. Any place where the PD output is a runt pulse will have a deadband (or perhaps cubic) characteristic.

The gain asymmetry of a PFD is useful for sideband selection in an offset loop--it can't lock up on the wrong sideband because the loop gain is way too high and it oscillates if it gets near there. Switching the sign of the feedback loop gain lets you pick LSB or USB reliably, which is much harder with an analogue PD.

Cheers

Phil Hobbs