Every fab publishes a spec for electromigration. Basically it is a
>current density limit, though they write it up based on the width of
>the metal. [The fab knows the metal thickness.]
>
>If you look at a die photo of the chip, at the edge of the driver you
>would see two fets feeding a metal bus in the middle. For the next leg
>(fets), it's current must combine with the current from the previous
>fets, so the fet stripes get smaller and the metal gets wider.
>
>Regarding elecromigration in general, I can plead ignorance to the
>physics. I know that once the mechanism starts, the metal line goes
>down hill fast. That is, the metal gets necked down a bit, which in
>turn increases the current density, which in turn causes more
>electromigration.
>
>The rules for electromigration are not particularly fair, and of
>course the designer doesn't get to vote on it. The fab generally bases
>the spec on a minimum width line, which assumes a bit of overetch,
>mask error, etc. If you are building a power device, you will not be
>using minimum width lines.
>
>The electromigration specs do allow for duty cycle. That is, you can
>design for the average current IF (big IF) the pulse lasts less than
>some mysterious time period. If you look at the 7219 "firing order",
>it pulses from side to side to give the power buses time to "relax".
>That is, if there are two paths to say ground, use one path then the
>other.
Thanks, that's quite interesting. Is that time period of the order of hundreds of usec or much less?
Best regards, Spehro Pefhany