Re: Digital Question

Sep 23, 2008 3 Replies
A

Jim Thompson wrote in news: snipped-for-privacy@4ax.com:



> I need to convert a _slow_ moving analog signal to "1" or "0",
> depending on whether it is above or below the digital threshold
> (CMOS).
>
> Problem: If I go directly into a gate or D-input of a flop I can get
> substantial overlap current rail-to-rail.
>
> This is a very low current application.
>
> Any suggestions?

Suggestion: Modify the D flip flop so that the first stage is completely turned off except for a few ns before the clock edge. This should result in ~0 current regardless of the input voltage at all times except when you actually need to sample the input.


If the clock frequency is low enough, this should result in some power saving.


Regards, Allan


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B

That's an interesting approach. However, if the clock frequency is "low enough" then it's going to be difficult to generate the "few ns before" enable signal.

Bob

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A

"BobW" wrote in news:W96dnSDDoL3xhETVnZ2dnUVZ snipped-for-privacy@giganews.com:

Delay the system clock by a few ns. Use this delayed clock as the flip flop clock. The system clock now leads the flip flop clock by a few ns.

The concept is not difficult. That shouldn't be meant to imply that the actual implementation is trivial though. I expect the hard part is convincing the EDA tools to do what Jim wants to do.

Regards, Allan

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M

TVnZ2dnUVZ snipped-for-privacy@giganews.com:

.
e

I like this solution. Design the flip flop so the first stage is just an inverter with a mux integrated into it. That is a string from top to bottom of P P N N. Gates of the top and bottom fets form the inverter. Feed a split phase gate drive to the other fets to do the sampling. I think the logic guys call this a gated inverter. The output signal can then be transfer to a static latch to hold the signal.

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