My preferred oscillator basically is...
but without the attenuator to avoid the ESD diodes... since my custom stuff has no ESD diodes on the internal nodes.
Also the inverters are single stage instead of the 3-somes built into the 74HC04's
U1A, in my designs, is often an NMOS device plus a current source pull-up, to minimize power consumption.
In a recent RFID tag design, a 2MHz clock runs on 1uA ;-) (1.2V supply.)
...Jim Thompson
I forgot to mention... without ESD diodes acting as clamps, this oscillator is quite insensitive to power supply value. proof is left as an exercise for the student ;-)
...Jim Thompson
We hardware dudes must live with what we's gitten in them thar trading post in Thief River Falls.
Yeah, can't get there with discretes. But close. AFAIR my record stands near 10uA at 13.56MHz.
That was given as the prefered design in National's "CMOS Oscillators" appnote in the 1981 4000 book.
Can you explain that? No attenuation means you don't get overshoot? That seems backwards.
My sense is (by intuition but not analysis) that the positive feedback makes that possible. Right?
No attenuation means the free end of the capacitor can swing ABOVE and BELOW rails without clamping.
Yes.
...Jim Thompson
That makes sense. When you said "without the attenuator" it sounded like you would omit R4 and R5 in a chip design, but that's where you need it most, where there are no diode clamps.
No. There's no reason you can't go above VDD and below ground with the gate voltage.
Run the numbers, then you'll see how VDD falls out.
...Jim Thompson
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