Hello, I've designed a simple R/C-Oscillator with a MC14060 (ON-Semi) C-MOS Logic IC. It's easy to calculate withe the formula f=1/(2.3*R*C) But I can't find information on the tolerances for this frequency in the datasheet. I know it will be quite a lot. I guess 30 to 40%? But to really know if I can handle this, I need to know what exactly the manufacturer guarantees. Do other manufacturers (TI, National, Intersil) have more information? Thanks in advance, Bernd
c IC. It's easy to calculate withe the formula f=3D1/(2.3*R*C)
datasheet. I know it will be quite a lot. I guess 30 to 40%? But to really = know if I can handle this, I need to know what exactly the manufacturer gua= rantees.
It's basically about the R/C exponential decay hitting the C/MOS gate thresholds, which are typically guaranteed to be somewhere in the interval between one third and two thirds of the difference between the supply rails.
Schottky gates have more tightly specified thresholds, and a comparator can be set up to be much more accurate again (to the point where noise on the supply rail can become the decisive source of uncertainty).
It's easy enough to do a worst case design. ln 0.333 is 1.099, ln
0.666 is 0.4065 while ln 0.5 is 0.693.
1.099 + 0.4065 =3D 1.5064
2 x 0.693 =3D 1.39
which is a 10% range. Claim +/-5% and you'll probably be in the right ball park. The distribution of frequencies won't be Guassian - there'll be more fast oscillators than slow ones.
For extra credit, throw in the difference between the output impedance of a CMOS gate connected to the positive rail - the P-channel output transistor - and the output impedance of the same gate connected to the negative rail (the N-channel output transistor).
It's easy to calculate withe the formula f=1/(2.3*R*C)
datasheet. I know it will be quite a lot. I guess 30 to 40%? But to really know if I can handle this, I need to know what exactly the manufacturer guarantees.
It depends on the tolerance of the parts used, and the temperature. If you want accuracy, use a crystal with it.
It's easy to calculate withe the formula f=1/(2.3*R*C)
datasheet. I know it will be quite a lot. I guess 30 to 40%? But to really know if I can handle this, I need to know what exactly the manufacturer guarantees.
Tolerances: Start with the Rs and Cs, and apply those to the circuit equation. The circuit itself can do good or bad: a phase retard circuit feeding the equivalent of a comparator adds in the uncertainty or tolerance of the comparison level. This is for starters.
gic IC. It's easy to calculate withe the formula f=3D1/(2.3*R*C)
e datasheet. I know it will be quite a lot. I guess 30 to 40%? > > But to r= eally know if I can handle this, I need to know what exactly the manufactur= er guarantees.
This is true as far as it goes. For a more detailed discussion see
formatting link
which brings out one of the nastier features of the oscillator circuit recommended in the MC14060 data-sheet - the gate input goes outside the rail, and if you rely on the MC14060's catching diodes to clamp the voltage to the rails, you are injecting current into the ic's substrate, which can be a bad idea.
If I get around to it. I'll model the recommended MC14060 oscillator in LTSpice and post the schematic.
Logic IC. It's easy to calculate withe the formula f=3D1/(2.3*R*C)
the datasheet. I know it will be quite a lot. I guess 30 to 40%? > > But to= really know if I can handle this, I need to know what exactly the manufact= urer guarantees.
?
Here are the LTSpice models with a 50% threshold - best case - and a
67% threshold - worst case.
Version 4 SHEET 1 880 680 WIRE -32 160 -192 160 WIRE 64 160 -32 160 WIRE 176 160 128 160 WIRE 272 160 176 160 WIRE 384 160 336 160 WIRE -192 208 -192 160 WIRE -32 208 -32 160 WIRE 176 208 176 160 WIRE 384 208 384 160 WIRE -32 320 -32 288 WIRE 176 320 176 288 WIRE 176 320 -32 320 WIRE 384 320 384 272 WIRE 384 320 176 320 WIRE -192 432 -192 272 FLAG -192 432 0 SYMBOL cap 368 208 R0 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL res 160 192 R0 SYMATTR InstName R1 SYMATTR Value 43k SYMBOL res -48 192 R0 SYMATTR InstName R2 SYMATTR Value 430k SYMBOL Digital\\inv 272 96 R0 WINDOW 3 52 30 Left 2 SYMATTR Value Ref=3D2.5 SYMATTR InstName A1 SYMATTR SpiceLine2 Vhigh=3D5 Trise=3D40n Tfall=3D40n Rout=3D1k SYMBOL cap -208 208 R0 SYMATTR InstName C2 SYMATTR Value 10p SYMBOL Digital\\inv 64 96 R0 WINDOW 3 52 30 Left 2 SYMATTR Value Ref=3D2.5 SYMATTR InstName A2 SYMATTR SpiceLine2 Vhigh=3D5 Trise=3D40n Tfall=3D40n Rout=3D1k TEXT -184 96 Left 2 !.tran 0 20m 0 10n uic TEXT -192 64 Left 2 !.ic V(n001)=3D0
This oscillates at 1050Hz
Version 4 SHEET 1 880 680 WIRE -32 160 -192 160 WIRE 64 160 -32 160 WIRE 176 160 128 160 WIRE 272 160 176 160 WIRE 384 160 336 160 WIRE -192 208 -192 160 WIRE -32 208 -32 160 WIRE 176 208 176 160 WIRE 384 208 384 160 WIRE -32 320 -32 288 WIRE 176 320 176 288 WIRE 176 320 -32 320 WIRE 384 320 384 272 WIRE 384 320 176 320 WIRE -192 432 -192 272 FLAG -192 432 0 SYMBOL cap 368 208 R0 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL res 160 192 R0 SYMATTR InstName R1 SYMATTR Value 43k SYMBOL res -48 192 R0 SYMATTR InstName R2 SYMATTR Value 430k SYMBOL Digital\\inv 272 96 R0 WINDOW 3 52 30 Left 2 SYMATTR InstName A1 SYMATTR SpiceLine2 Vhigh=3D5 Trise=3D40n Tfall=3D40n Rout=3D1k SYMATTR Value Ref=3D3.33 SYMBOL cap -208 208 R0 SYMATTR InstName C2 SYMATTR Value 10p SYMBOL Digital\\inv 64 96 R0 WINDOW 3 52 30 Left 2 SYMATTR InstName A2 SYMATTR SpiceLine2 Vhigh=3D5 Trise=3D40n Tfall=3D40n Rout=3D1k SYMATTR Value Ref=3D3.33 TEXT -186 98 Left 2 !.tran 0 20m 0 10n uic TEXT -192 64 Left 2 !.ic V(n001)=3D0
which oscillates at 997Hz.
Less difference than my first sketch of a worst case analysis suggested.
Logic IC. It's easy to calculate withe the formula f=3D1/(2.3*R*C)
the datasheet. I know it will be quite a lot. I guess 30 to 40%?> =A0> =A0B= ut to really know if I can handle this, I need to know what exactly the man= ufacturer guarantees.
?
Interesting - if implausible - story. As far as I know, charge carriers injected into the substrate via the protection diodes don't do anything different from charge carriers that get there from anywhere else.
Charge carriers that get into the gate oxide are another - but here totally irrelevant - story.
If the MC14060 got messed up by current going through the protection diodes, we'd have heard about it by now.
Gnaw, that's "hot carrier injection", which has something to do with excessive voltage drop through a channel, with a nearby thin-oxide gate. Nothing to do with substrate diodes. High energy electrons jump the oxide, causing gate leakage. If the gate happens to be a floating hunk of metal (as is used in floating-gate EPROM structures), the gate keeps a permanent charge.
Tim
--
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IC. It's easy to calculate withe the formula f=1/(2.3*R*C)
datasheet. I know it will be quite a lot. I guess 30 to 40%?> > But to really know if I can handle this, I need to know what exactly the manufacturer guarantees.
No. It's driven up and down via current _mirrors_.
You'd think, but I can't confirm that for this part, which also claims hysteresis in those thresholds.
You're sort of stuck with that unless you added a rather elaborate clamp that occurred before the current mirror goes "soft" at the bottom of the cap travel.
They'd failed to properly convert my MC4024 design CMOS ;-)
It's allowed for here with "plugs" to conduct to the ground pin.
Bwahahahahahahaha!
Don't know what you're saying there. What abuse did you do ?:-)
More than a month ago I started a fully behavioral model of the 4060, but got side-tracked by real (as in paying) work.
I still plan to finish it, since it presents some interesting circuit features to figure out with behavioral implementations. ...Jim Thompson
--
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| Analog Innovations, Inc. | et |
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| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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I love to cook with wine. Sometimes I even put it in the food.
IC. It's easy to calculate withe the formula f=1/(2.3*R*C)
datasheet. I know it will be quite a lot. I guess 30 to 40%?> > But to really know if I can handle this, I need to know what exactly the manufacturer guarantees.
Regarding injected charge, be advised that each time, some gets trapped and the the accumulated charge acts as an input voltage and
*permanently* latches the gate; input voltage then is "ignored". The fix? Anneal the damage in an oven; perhaps 135C will do the job.
Logic IC. It's easy to calculate withe the formula f=3D1/(2.3*R*C)
the datasheet. I know it will be quite a lot. I guess 30 to 40%?> =A0> =A0= But to really know if I can handle this, I need to know what exactly the ma= nufacturer guarantees.
n?
As opposed to what's shown in the data sheet, and gives the right answer when modelled with LTSpice.
Really? The Motorola data sheet shows just one input with hysteresis - "Out 2" on pin 9 - which take the clock output from the oscillator and cleans it up before feeding it into the counting flip-flops. It's thresholds don't come into the calculation of the oscillator frequency.
As you'd expect in a part where the recommended oscillator circuit drove one of the inputs outside the voltage rails.
It's been done and posted - Jim has got me killed-filed so he doesn't realise that he's made an ass of himself again. The LTSpice model gives pretty much the right frequency - a bit too fast with an exactly 50% threshold, and very slightly too slow with a
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