CD74HCT165 question

From the data sheet at:

Description The Harris CD74HC165 and CD74HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0®Q1®Q2, etc.) with each positive-going clock transition. This feature allow parallel- to-serial converter expansion by typing the Q7 output to the DS input of the succeeding device. For predictable operation the LOW-to-HIGH transition of CE should only take place while CP is HIGH. Also, CP an d CE should be LOW before the LOW-to-HIGH transition of PL to prevent shifting the data when PL goes HIGH.

This says basically that:

CE (active low) is the 'chip enable' signal. PL (active low and latching on the rising edge) is the 'load data' signal. CP is the clock signal (rising edge triggered).

The 74HC165 will only send a new data bit for each positive going transition of the CP input. Thus something is going to have to make the CP signal change. This is a clock of a sort. It does not necessarily have to have a fixed frequency.

You could connect two outputs of the microcontroller to PL and CP and an input to Q7. Use the output tied to PL to tell the 165 when to load data. I.e. Normally PL is high, then send it low and back to high. Then use the output tied to CP to shift the data to Q7. Then use the input from Q7 to read that data. I.e. Normally CP is low, then send it high and then read a data bit from Q7. Send CP back low. Repeat this process for a total of eight times to read D7 to D0.

Dan

Of course! How do you think the data gets out?

You'd better go back to the professor and have her explain the lesson again.

Good Luck! Rich