I've been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad.
A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routing and vias in that space. The current layout has 7 vias under this package.
An alternative package is a 16 pin QFN, 4 x 3.5 mm. The part is much smaller, but it has a thermal pad that occupies nearly the entire space under the part, leaving no room for vias, or even routing. So it has to all be done outside the pad footprint which is 4.3 mm x 4.8 mm.
Looking at a layout, it seems to me to be pretty much be a wash, at best. The pads are now on 0.5 mm centers making it hard to add vias staggered on just two rows, given 6/6 mil design rules and 24 mil via pads. Pretty much all the saved space gets eaten up by moving the vias outside the pad outline.
Are there other reasons to use QFN packages for parts that don't have thermal issues? I've never heard anyone say they have particular issues with QFN devices, but are there any real advantages other than getting power through the thermal pad?