QFN footprint PCB layout

The best authority is the chip manufactuer, which you don't tell us.

There are some app notes around for such things, but each device can have it's own characteristics.

The pad may be there for thermal coupling, really low noise ground coupling, or both.

Tell us what it is, we might be able to help.

Cheers

PeteS

Usualy the QFN or TQFN with exposed pad needs a multilayer ground with a large numbers of vias (15-20) between top and bottom side to evacuate the heat. Any evaluation kit from Maxim using QFN for example is showing how to do it.

greetings, Vasile

Copper the same size as the pad. Solder mask aperture the same size as the pad. Solder paste stencil aperture about 60% of the area of the pad, in order to not put too much paste on. If it is a small pad then just make a single aperture in the centre. If the pad is big then make multiple apertures in a windowpane pattern such that the total area is about 60% of the pad but no one aperture is too big.

If the chip is big and power hungry and the pad is used as a heatsink then put lots of vias in it down to the groundplane. If not then just a few will do, if indeed it needs to be grounded (mostly they do).

I think Xilinx has a reasonable app note on the subject.