I'm looking to buffer a clock oscillator to improve fan-out. In my application, skew is not important, but symmetry is - I need a 33MHz clock with 40% to 60% duty cycle. My clock oscillator is guaranteed to be between 45% and 55%, so my buffer must have (TPLH - TPHL) < 1.5ns in order to be safe.
My questions are: can I expect the low-to-high propagation delay of a CMOS device (ALVC244) to be very close to the high-to-low delay? In this type of device, what causes differences between TPLH and TPHL? Is the phenomenon temperature dependant?
Any pointers would be much appreciated.