Analog neagtive delay generator - please help

What kind of signal do you want to delay? If it's a periodic clock,
all sorts of phase shifters or delay lines will work.  A 0.75T delay
line looks like a -0.25T delay. Or invert phase and delay 0.25, same
result.

If it's a general signal, it's impossible.

John

Well, so much for the stock market investment machine I was going to build!

Even a small negative delay could be put into a feedback loop to get
arbitrary long negative delays, enough to see the Drudge Report a week
in advance.

John

John Larkin a écrit :


Cool. So with a small TLine put in a feedback loop will give looong
delay line? And maybe varying the loop gain will make the delay variable?

Better patent that before others do.

Or a PLL.


Ayup.

The problem I am trying to solve is :
Consider an analog PLL and the reference signal is pure sinusoidal. In
a "locked in" mode, the VCO output will be a sinusoidal signal of
exactly same frequency as the reference signal, but has an added phase
(basically delay),
because of the way the VCO works. So is there a way to remove this
phase ??


On Mar 26, 9:20 pm, John Larkin

 > The problem I am trying to solve is :
 > Consider an analog PLL and the reference signal is pure sinusoidal. In
 > a "locked in" mode, the VCO output will be a sinusoidal signal of
 > exactly same frequency as the reference signal, but has an added phase
 > (basically delay),
 > because of the way the VCO works. So is there a way to remove this
 > phase ??
 >

That depends on your phase detector.  If you're talking about a classic
mixer-style phase detector that returns zero error when the VCO is 90
degrees off from the reference -- yes.

So you can solve that, either by making a network that phase shifts the
VCO by 90 degrees before applying it to the phase detector, or -- if
your reference is also a pure tone -- by using a digital reference
detector that returns zero error when the phases match.

Thanks for the insight. I do remember the phase detector output vs.
phase graph fom Paul Gray's book. However,
I wish to verify a few more issues:
1. A reference signal and 90 degree phase shifted VCO output, when fed
into the phase detector produces a zero error - so what signal is
being fed into the loop filter ??
2. Suppose I split the raw VCO output (just before adding the 90
degree phase) and try to use it for something - what  is the phase
difference between this and the reference input the the phase
detector ??

Thanks for the helpful insight and suggestions.

Firstly, what is 'delay locked loop'?

When one needs a signal and a delayed copy of that signal, one uses
a delay line (simplest is just a long cable).  Then, the events
on the signal cable are occurring prior to those on the delay line,
and you can refer timings to the delay-line-output and
call the direct signal 'negative delay'.   That's  how an
oscilloscope can trigger on a pulse and still show the
lead-up to the pulse on the display.

It is a delay line with a variable tap, or some sort of variable RC
delay, that is controlled in a similar manner to a PLL to get controlled
delay.

They're way popular in FPGAs these days, to de-skew clocks, double
clocks (by XORing a clock with a delayed version), have controlled phase
differences between clocks, and other useful things that you need if you
want to build really, really, really fast logic on a chip that's only
really, really fast.

It's a delay line in the feed back path of an oscillator.  A "digital PLL", if
you will.

A very common instance of this is 'advanced sync' used in television
to make a video source create a signal early so by the time it goes
through processing it's at the desired time. As Larkin said, it only
works with a periodic signal. AND, that 'advanced' signal is only
delayed 'almost' 1 time period back so it seems advanced. It's not -
so Tim Westcott can't have his investment machine.

GB2%

Bummer!