Programmable clock pulses from FPGA

The fpga programmers hang out on comp.arch.fpga

Using an FPGA to generate programmable clock pulses involves setting a programmable down counter accumulating clock edges from a stable clock source, usually as fast as possible.

You then use the over-flow output from this counter to generate the transitions on your programmable clock output.

The last time I did this, I committed a large chunk of fast static RAM to holding a long list of data defining both the number of clock tics between the transistions on the programmable output and the output level after each transition. In principle you don't need to specify the level after it each transition, just the initial level, but this is vulnerable to spikes and slightly less flexible.

Modern FPGAs can be programmed so that most of the cells act as static RAM.

Maximum clock frequencies were running around 500MHz when I last looked, but that was quite a while ago.

A 500MHz clock limits the placing successive edges to 2 nsec increments. Finer resolution can be produced with programmable delay lines - in the simplest implementation within an FPGA, the delay through an individual logic gate becomes the minimum increment.

If you recognise that the propagation delay between individual logic gates is going to show some kind of production tolerance and that routing delays around the FPGA can be appreciable you can go a bit further.

My system was planned to use self-calbration to compensate for temperature dependent changes in these kinds of propagation delay by using these delay elements to set up pulse width moduated waveforms whose mark-to-space ratio depended on these delays; put such a waveform through a low pass filter and digitise the DC level to - say

- 16-bits and you can deduce the actual mark-to-space ratio with a precision only a few bits lower.

-- Bill Sloman, Nijmegen

One idea for generating clock pulses is to use the DDS concept and some additional logic, like I've developed:

It is for Spartan3E starter kit, but should work with other boards, too; you don't need the analog and CORDIC part for your clock pulses. When I have some time, I plan to enhance it for generating signals with less jitter.

A simpler example, for easier learning how DDS works:

All examples includes the Impact programming files, but you have to create your own for the Spartan3A and other UCF files (the UCF files should be provided by the manufacturer of your development board). There are good tutorials at Xilinx how to use their non-intuitive software. And as Bill wrote, comp.arch.fpga is a good place to ask, if you don't understand something and the Xilinx support is helpful, too.

Hi,

I really appreciate your reply. But I don't know how to create this UCF file. I am sorry to ask these kind of questions but I am a beginner for this kind of project. So I am bit frustrated, therefore, i request you to kindly guide me in detail or any material that can guide me in detail about downloading a programme to Development Board.

Best Regards, Anas.

Please tell me the name and company of the development, in order to avoid it in future. A development board without a working example project with all necessary files, or at least a step-by-step PDF, or some website where you can download it, would be no fun.

Hi,

I got my board from Xilinx, it is Spartan 3A board and the FPGA number is XC3S700A. I would really appreciate if you can help me on that.

Best Regards, Anas.

Sometimes it can be difficult to find something at the Xilinx site. Take a look at this webpage:

The user guide describes the board. UCF files and design examples can be found at this page:

On the CD with my kit was a step-by-step PDF how to use ISE and how to create, synthesize and upload your first design, I didn't found it on the Xilinx page. You should really ask in the comp.arch.fpga newsgroup, if you need more help, because there are some more people who have the same board (among other things I have the Spartan3E board).