I am making a 4 layer PCB and have multiple supply rails (12V, 5V, 3.3V, 2.5V, 1.2V). I have put all of the supplies on the internal layer2 as polygons, some of the polygons look like large "C" shapes, is it better to close these polygons to make them loops, or is it better to leave them open? I think the loops will have lower inductance than open branches, but not sure if they are recommended over using branches.
Also are loops better than branches for common mode noise immunity?
Assuming an adjacent ground plane and a scattering of bypass caps, it generally makes no difference. Loops are arguably a bit better, but not much different in most cases.
I don't understand that question.
We tend to use L2 as a solid ground plane, so that topside parts are maximally shielded and topside controlled-impedance traces are all working against a nice quiet ground, and to minimize part-to-ground impedance. So L3 gets the pours.
It is often the resistance more than the inductance that matters. There is a significant capacitive connection from all points on the polygon to the ground layer plus any bypass capacitors you've added. Large currents and any resistances can combine to create noisy supply voltages.
A lot depends on the frequencies that matter to the circuits. For most op-amps, the PSRR falls off with frequency. On many it is the minus rail that matters. If this is the case in your application, you can focus on the part that matters.
The PCB I am making experiences high frequency common mode noise transients through isolated ferrite transformers that power a SMPS, so I am wondering about ways to increase the common mode load of the circuit so that the common mode noise transients are attenuated more. I am using common mode chokes on the transformers, before I added these I was getting microcontroller/FPGA resets due to the mosfet switching transients being coupled through the ferrite transformers. I am wondering if supply loops or branches are more immune to these common mode noise transients, and also any other techniques that can increase the common mode load or common mode rejection of the PCB, beyond using a ground plane, bypass caps etc.
If everything including the nearby sheet metal is rocketing up and down with some common mode signal, things will work. It is when there is a path for the high frequencies to pass through the circuit and and find their way back to the supply that there is trouble.
If you make all of the entry and exit points of the circuit all grouped at one location the currents won't tend to flow through the PCB as much. If the supply is under your control, you are far better off trying to prevent the stuff from getting sent to the circuit board. Placing RF beads on the input side of the supply can help. What you currently have is:
The beads appear in parallel as far as the noise getting to the circuit is concerned. You don't want good quality inductors because at some frequency they will resonate with Cx.
A power pour should be equipotential with the adjacent ground plane, at all points, regardless of its topology. At high frequencies, plane-plane capacitance takes care of that. At lower frequencies, the scattered bypass caps glue them together. So power pour patterns shouldn't be affecting any common-mode problems you are having elsewhere.
4 layer board, 5 supplies, power pours starting to look strange. I would recheck the floor planning first. If no help was found there i would to move one supply to another layer.
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