4-layer - which layer for ground, power?

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Generally speaking, your full plane layers should be internal. Keep in mind you can always 'bore through' for a signal that really needs to be internal.

If you have no major noise sources, then use the inner layers. Incidentally, the outer layers of a 4 layer board (and lots of other layers in really dense boards - I have done 28 layers) are on prepreg - they are almost literally glued to the board :)

The inner layers on a 4 layer board are on core material.

Like this:

Outer layer ----------------- Cu Prepreg -------------------- Inner layer ------------------ Cu Core (FR4 or whatever) Inner layer ------------------ Cu Prepreg --------------------- Outer layer ----------------- Cu

Note that I fill unused areas of the outer layers and tie it to ground (usually). Most board houses will automatically fill the outer layers to a great extent to prevent warp.

Cheers

PeteS

Reply to
PeteS

Something you may not have thought about. You need symmetry relative to the center of the board stack. If you put the planes toward one side, the board can warp significantly. Your fabrication house should have experts to advise you on what works with their process. mike

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Reply to
mike

Well, I usually mount my components on the outside layers of the PC board, so that's where my signal tracks go.

You're free to mount them in the inside layers of the PCB if you want :-).

Tim.

Reply to
Tim Shoppa

Ah, yes. I'd read about this, and promptly forgot about it.

I've seen comments about hatching the fill instead of using a solid plane, also for warping reasons - is this a valid concern?

Reply to
Richard H.

Point taken. This design is 4-6 devices on a ~40-line bus, so there's no hope of keeping the traces on one layer anyway, but keeping to 2 layers for signals means one set of vias for each device, instead of two. Two layers is fairly compact, but the power and ground fills are pretty chopped up, so that's why the 4-layer interest.

Reply to
Richard H.

Good points, thanks. It seems some more creative layout is in order to compress the 2-layer signal layout, then add the center power planes, rather than double the vias and spreading the signals across 3 layers.

So, who are good shops for 4-layer protos? (We're in the US.)

From dredging the back of trade mags, it seems Sierra Proto Express has the competition beat on pricing - for a 4x6" board, they're about $125 for batch of 2 boards. Everyone else ranges $200 - $400 per batch minimum. Is there a catch?

Reply to
Richard H.

That's a question for your vendor. Problem is that they ship you a flat board. You run it through reflow and it warps. Still not much problem until you install it into a package designed for a flat board that straightens it out. And your SMT parts start cracking...just after you shipped it... mike

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mike

Assume you have a pair of bus traces above a ground plane. All is good... Now, cut a slot in the ground plane under the traces as you would to try to put traces on that plane too. You've just installed a coupled inductor in series with your bus traces. All is bad. You'll find pattern dependent errors that will drive you nutz if you're lucky enough to find the symptom before your customer sends it back 'cause it don't work. You can usually "get away" with some of this stuff...it's all a tradeoff. mike

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Reply to
mike

Keep in mind that some board houses make the thickness between

2 and 3 smaller by default. More capaciance is good for PWR/GND, not so good for signals.

Cutting up the power/ground plane with traces isn't always bad. a few very short traces to jump over problems can make a huge difference in the routability of the project.

Reply to
Guy Macon

Richard, Mostly as an experiment, I once did a modified version of your "B". We already has some boards of the conventional type with the signal layers being 1 & 4. So, without changing the placement, we made up some boards with the signal layers as 2 & 3. Ground was 1 and VCC was 4. What helped was that we snuck some short signal traces on layers 1 & 4. Audits showd that all crosstalk numbers dropped by a factor of two by having buried signal layers; possibly due to slower rise times. Anyhow, we went to production with Plan-B, and there were never any problems. This was a memory board with through hole DRAMs. Not sure I would want to do it with SM.

Tam

Reply to
Tam/WB2TT

Or sometimes like this:

Outer layer ----------------- Cu

Inner layer ----------------- Cu Prepreg --------------------- Inner layer ----------------- Cu

Outer layer ----------------- Cu

Not so common on US-made boards, but you see it on some really low-cost/high-volume asian boards. Sometimes the only vias through that middle layer are component leads and the board is double-thick - because they are really a 2-layer board house that glues two 2-layer boards together to make a 4-layer board.

Reply to
Guy Macon

I don't think cross-hatching would effect EMI performance very much, as long as the hatches are small. But I don't really see any reason to do it, either.

It seems to me that filling the surface layer of a SMT board with a ground pour is inviting disaster, unless the surface layer is very lightly routed. You are just creating a whole bunch of undesirable current paths for ground. And you have to meticulously go around and make sure each island is tied to the solid ground plane. And it may adversely effect the trace impedance of surface traces.

When I designed high-density, 12-layer, single-board computers, the EMI guys certainly never suggested that we put copper pours on the surface layers. And these EMI guys seemed to know what they were doing.

Just my $0.02

--Mac

Reply to
Mac

As I said they were short traces. Basically crossovers to help out the autorouter.

Tam

Reply to
Tam/WB2TT

Here is an example of how I made use of four layers on a recent design.

I had a small board set produced that was assembled with two of the boards stacked up with only a small space between them. One had very high gain, high impedance (therefore sensitive to capacitive noise) amplifiers on it and the other had a microprocessor and some logic. I put all the analog stuff on one side of the board with only one cross under on the other side at the output end of the amplifier chain. It was a nearly via-less thing of beauty. The only holes were for connections to power and ground planes. The layer below the amplifiers was a ground plane with its potential held half way between the battery rails, regulated by an opamp output. The second buried layer was split to carry both positive and negative rails. All of the (few) logic control signals ran on the bottom layer, and connected to the control pins of some CMOS analog switches by passing through an island (in the signal ground layer) tied to either positive or negative rail voltage so that they had very little capacitance to the ground plain. This kept the ground plane very free of any high frequency currents. One point (a fat via) on the ground plane was the reference point (star ground) for all the high gain nodes. This layout plan shielded the amplifiers very well from under side noise.

To keep the micro from contaminating the amplifiers, I used the two layers on the facing side of the micro board for positive and negative rails (there is no ground plane connection to the micro board). I used the top and second layer for all traces on the top side and all components are mounted there. The only sources of varying e-field on the under side of the micro board (above the amplifiers) are a few, small vias surrounded by supply voltage.

These boards are made in a strip and break apart. They are smaller than a cigarette pack, so warping is not a problem.

I am very happy with the noise coupling on this set.

Reply to
John Popelish

"Tim Shoppa" a écrit dans le message de news: snipped-for-privacy@z14g2000cwz.googlegroups.com...

Or if you insist on mounting the components outside you'll have to have one via per pad. You don't have those when your signal tracks are one the outer layers.

Plus components pads + signal pads exit vias + routing vias = lots of holes in your outside ground/power planes, i.e. probably more EMC problem than solved.

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Thanks,
Fred.
Reply to
Fred Bartoli

All I knew was that the hand built prototype sort of worked if you held your mouth just right and it was a Wednesday, and the first pass layout (with little hand holding) worked fairly well, most of the time. So this was the third attempt to prove that the circuit could work, reliably and I pulled out every stop I could get hold of.

The only problem I am having with this layout, now is that the board is sensitive to humidity. Evidently, the fiberglass absorbs moisture for about a week after it is exposed to an increase in relative humidity, and this increases the capacitance of the component pads to the buried ground layer. This increased capacitance seems to be nonlinear, also. Damp glass seems to be a crappy dielectric.

I am now going through various simulations with these parasitics explicitly modeled to find out where the problem may be centered and what alterations may minimize it.

But after a week in dry air, the present layout works just great!

Reply to
John Popelish

..and allows the board house to etch more boards with a given amount of chemicals. Nice to help the environment a bit while making the board better.

Reply to
Guy Macon

Yep. Exactly the problem here - fine pitch, most pins used.

By the time all the traces are routed away from the chip, there's not much room left to get 0V in there. Despite tying them together via the bottom layer, it's coming up short.

Thanks, Richard

Reply to
Richard H.

IME smt boards tend to be mostly-routable on the smt component layer (if you place parts right, and suitably jiggle nets). my 4-layer pcb's have all been made with a 2-layer inner core, I use mid-layer 1 as a solid 0V plane (I set up via placement rules to ensure the 0V plane can flow between all vias). This keeps the 0V plane as close as possible to the components, maximising capacitance but minimising inductance. I am looking at using a 6-8 layer board for my next job, specifically to reduce the top-mid1 separation, thereby reducing L even further....

with smt boards the pads are often bigger than the components, so dense smt boards tend to have really patchy 0V planes on the same layer, even without interconnecting traces. I wouldnt rely on that for a ground.....

And like others have said, when done I pour an 0V plane on every layer - better EMI performance, evens out Cu density to minimise warping etc. from an EMI perspective, cross-hatching pours is a bad idea, and gets worse as the cross-hatch grid gets larger.

Cheers Terry

Reply to
Terry Given

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