I guess we are (but the bank and the boss enjoy the humor). At least my stuff goes *poof* with the rails at 1.7V, so using spice isn't all that interesting at 1.7V. ;-)
Does your charge-pump operate with 1.7V rails? ;-) .25V?
I chose .25V because one POR circuit requirement was for an active low to be guaranteed above a .25V VCC, until the power supply was within spec and stable for some period. Forcing a low voltage with a .25V rail, under worst case conditions, wasn't an easy thing to guarantee.
I assume that these people were the same ones who would do this work.
By any chance do you work for Maxim?
There are quite a few chips (such as comparitors) that are well characterized at low voltages.
You can often power parts of the reset circuit from the input side of the regulator to ensure that it gets powered before Vcc appears.
If you want to be very sure of the Reset/ staying low during the supply upswing, you can use a JFET as the output switch.
Some micro controllers have the reset circuit built in. If you follow the manufactures recomendations on most of those, the results are correct.
The best and easiest way to do a brown out protection is to have the brown out comparitor turn off the main power. If the Vcc regulator is broken or the batteries too dead, this is the best thing to do. Running correct code to some random point and then restarting it over and over is no better than running bogus code.
Funny you didn't include the power switch bounce case and the brown out case in your suggested checks. These are more likely in real life.
Well, it was 30 years ago, so no low Vt's. It wasn't my circuit, but IIRC Germanium NPNs were the only solution that worked, barely. (and what a PITA to get them approved, even then). ;-)
Seems reasonable. I guess with a 0Vt you should be able to get a decent POR circuit.
Well, I'm one of those humorous digital guys, so what do I know? ...but if I had to guess, I'd guess a mirror.
Well the funniest post was one suggesting that I work at Maxim, seeing as how I just spent over 3 years at National Semi and that I consider Maxim to be a despicable company (although they do have a few nice parts, if you can get ever get them).
I guess I was trying to say that the existence of an entire product line at Maxim suggests this function is one worth paying for. The fellow who posted (correctly) that I didn't even mention switch bounce was right on the money as to why a cap and resistor can get you into trouble. Of course if the chip at least has POR circuitry and a POR reset pin then the cap and resistor may be fine, as long as the datasheet says so.
Similarly I was not very clear about the process used-- I never meant to say you need an analog process. I am just saying the circuit needs to be designed at the transistor level. Digital simulators can be as simple as on/off indication with a little timing thrown in. That just is not enough when the power rails are all over that place. No, there are plenty of fine POR circuits done in CMOS for digital.
If JT has a circuit that he can vary process corners it looks like he understands the grief of doing a POR. I have worked with a lot of digital guys that just can't comprehend that gate-level SPICE just does not work when the rails are at 1.7 volts. Heck, Bob Pease would say that analog SPICE doesn't work much better (;^o)-
Hot-swap circuits are equally non-trivial. Did the card get stuck in for a millisecond, then yanked out, then stuck back in-- what is the state of all the circuits on both the mother and daughtercard.. ect ect ect
Many FPGA and CPLD circuits do not become sane until the supply voltage reaches and stays above some voltage. It would be nice if the power on reset chips also could be used to force the SELF-DESTRUCT signal to ground and the EXPLODE-IN-FLAMES/ signal near Vcc until after the RESET is over and then glitch free connect them to the signals from the CPLD.
Unfortunately I just caught a part holding its output high until Vcc was high enough to be taken as logic high by a 74HC part. I've had to add and and gate to the system.
That reminds me of an 80c552 circuit I designed once. The Philips datasheet quite explictly stated that the port lines would go high when reset was asserted (and the clock was running!). But, as it turned out, that only applied while Vcc was within tolerance. When Vcc fell to about 2V or so, the outputs would go low, causing all sorts of mayhem.
I fixed it by gating the port outputs with a 74HC part.
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