528MHz clock level conversion

Take an inverter and place a relatively high value resistor from input to output... say 1Meg.

Then AC couple your sine wave thru a capacitor (~20pF) to the inverter input.

Output of inverter will be CMOS levels... maybe rounded, but at least CMOS ;-)

You might also want to look at differential receivers, such as the Fairchild LVDS products... some of these designs can easily do 1GB/s (500MHz).

...Jim Thompson

An SN65LVDS2DBVB would probably work that fast. Technically, the input common-mode range is 0.2 to 2.2, but they seem to work fine around ground. I use them, basically, as fast, cheap comparators. The output swings 3.3 volts in something outrageous like 420 ps. I'd suggest a source terminator resistor in series with the output. Output-to-input DC feedback could be used to servo the duty cycle to exactly 50%.

I've got a system with several of these, plus a lot more stuff, in the signal chain and I'm getting overall jitter of a few ps RMS.

Or an opamp, THS4302 maybe.

John

The SN65LVDS2 has the fastest LVTTL output rating I've seen, I think, and I've looked at A LOT of diff to single-ended buffers. But it's still only rated for 400MHz. May work but I'd have to bread board it first. The THS4302 looks like a winner, though. Its large-signal gain is flat way beyond

Rob

Agreed. It might not work that fast. If you do try it, please let me know how fast it will work.

TI has a nice eval board for the 4302. It's an amazingly fast and clean opamp

John

LVCMOS doesn't go near indeed. There are LVDS buffers, ECL, and some SiGe stuff, plus discrete

Rene

I'm a consultant developing proto/eval boards for a wireless chip company. Some things are out of my control. The RF synthesizer that generates the

Rob

Yes. One would have to try it to see how fast it will really go. The OP does have a big input signal swing available, relative to the LVDS minimum.

But hardly any voltage gain. Less than one in this case.

Oh, one could use a mmic here, too, and ERA-5 or something.

John

For RF / IF purposes.

You're struggling with capacitive loading of a high-Z signal source.

Hah! If you really need a 3.3V swing for some purpose (other than to drive logic gates), you could use a 50-ohm 1GHz RF power amp. A 3.3V p-p level is 1.2V rms, which is ~30mW into 50 ohms, or 15dBm. You'll get a slightly distorted sine wave with a 20dBm-capable amp.

Snort! Soooo, you'd be happy with a full 3.3V logic-signal square wave with say 200ps rise and fall time (that's 10% of the period)?

Never miss an opportunity for an insult, huh Fred?

I guess everybody who ever uses chips with different I/O level specs is an idiot.

John

Breadboard ? A lof of speed may be lost due to lacking design. A few nH here another few pF there ...

Rene

John, a signalling rate of 400MBPS means 200MHz, and both slopes used. No?

Rene

If an LVDS part, then perhaps a 65LVDS100 or 65LVDS101, the first being a 2GBit LVDS repeater, the second being a

Rene

This is a weird situation. Here's the history of how it got to this point. The company I'm consulting for is developing a wireless chipset. They've built a series of test chips over the last year to test various pieces of their design, and my job is to do the board designs and some FPGA work. The first test chip had 1.2V I/O. The Si4133 was already in the design when I entered the picture, and I am not responsible for the RF parts of the design. To get the 528MHz clock into the first test chip I used a very fast diff-to-LVHSTL buffer from ICS that output a beautiful 1.2V single-ended clock. But the rest of the 1.2V I/O (going to/from an FPGA) was a pain in the ass.

On the next and two subsequent test chips the clock input became 3.3V single-ended. I urged them to either go back to the 1.2V input or use a differential input for the clock, but they've kept it at 3.3V. I'm not privy to the reasons - I just have to make the boards work. I experimented with some things on the last board that did not work out, so this time I want to really solve the problem. I'm a digital guy and don't have a bag of analog tricks to fall back on, but I've gotten some good ideas here that I'll look into. Thanks to everyone who replied with suggestions.

Rob

All I can say is, sheesh!

That's what makes your requirement suspicious. You have mismanaged your component configuration somewhere along the way. There are synthesizer IC's that just produce 3.3V CMOS clock levels at 500MHz.

Heck, Win, a 3v p-p square wave at 600 MHz is just getting interesting!

John

Sounds like you are working for amateurs. Wireless chips, or chip sets, don't use external clocks.

They use an external XTAL at (typically) 16MHz, and PLL the whole she-bang.

Even on-chip, with no pin capacitances to drive, 500MHz is an upper limit for CMOS. I usually use some form of PECL until I get down to

...Jim Thompson

Oh, scratch the LVDS receiver. I tried one and it gets weird above about 300 MHz.

Opamp or MMIC, I guess.

I did cheat once and use an MC10EL89 to make a CMOS clock. Its output swings close to 2 volts p-p, and if you AC couple that and center up the swing...

John

John

For you perhaps, John, but not for RobJ.