PMOS device reversed

No problem, we do it all the time. Keep in mind, if the reverse ON voltage exceeds a diode drop, the MOSFET's intrinisic substrate diode will start conducting, in parallel with the ON FET. This is fine, except the diode usually has a reverse-recovery-time issue that can affect fast H-bridge switching, or example.

Thank you for your reply sir. (I am a fan of A-of-E!)

I know that the sync fet of a buck regulator is sometimes expected to reverse conduct during the dead time so I know that discretes can do that. I just wasnt too sure if it was safe to do so with a pmos device which is sharing the die with other components as in the case of an ic.

Thanks QQ

Thanks Graham, I was concerned about the same but I am not sure if it will or will not turn on any parasitic diodes given that all devices are sharing a common p-substrate. Any specific idea on what parasitics may be prone to turn on?

Thanks QQ

Yes, I agree it could be a problem. If you carefully monitor the chip's supply current with and without the FET's parasitic diode conducting, that may provide a clue.

Hmmmm . An IC ? You want to check if that reverse voltage is going to cause any other problems. It might turn on parasitic diodes in an IC with unpredictable results.

Graham

Hi Jim,

Thanks for your reply. Through my reading up on the net I was coming to the same conclusion but the information is quite hard to find. Would it help if this device was a "high voltage" pmos with a N buried layer? Would the N buried layer effectively cut off the vertical pnp transistor? (I read this somewhere..)

I dont understand. How will this help to cut off the vertical pnp?. My source is supposed to be connected to the highest potential already. Is it sufficient to connect body to source?

Will this problem occur in the case on NMOS device as well?

Thanks qq

Jim Thomps>

The "common p-substrate" will be at the body potential of all NMOS devices... desirably the most negative potential on-chip.

PMOS devices are built in an N-well, thus forward biasing the body diode will activate a vertical PNP.

If enough current flows to regenerate, this is called LATCH-UP.

PMOS devices that need to handle bi-directional currents usually have their well (body) tied to +VDD.

...Jim Thompson

Hi Jim

Okay I drew a picture and I see now that if the body is always connected to the higher of the two potentials then the base of the vertical pnp transistor is always at the highest possible potential. So the base is at a voltage higher than the emmitter at all times thus turning the vertical device off.

No I am not asking this..your original interpretation is correct. The "source" end (this device is assymetric) is connected to the body and the voltage at the source can go to a voltage equal to the highest available on chip voltage. So tying the body to a voltage higher than either source or drain is not an option.

Does having an N buried layer help in any way, to cut off the vertical pnp? This is a HV device which has an n-buried layer (whose function I dont know). The low voltage devices in the same process do not have buried layers.

Thanks qq

You originally indicated a desire to tie body to drain (rather than source), which would provide the possibility of forward bias.

However, if you were really asking, "Are source and drain interchangeable?"

The answer is yes (generally, some HV devices have different source and drain structures), PROVIDED body is always most positive.

Draw some pictures to envision how the junctions are arranged.

...Jim Thompson

Could you please explain why does it cut the pnp? What risk still exists?

I would like to but cannot because of confidentiality. Hope you will understand.

Thanks qq

Sorry missed this...there is a separate body connection but there is no available voltage that is higher than the maximum possible voltages at source or drain, to which to tie it.

Thanks qq

No separate body connection?

N+ buried layer _will_ cut the vertical beta, but I wouldn't count on it for safety.

Can you describe your application in more detail?

What situation forces you into the potential risk of a forward-biased body diode?

...Jim Thompson

Richer doped base _generally_ loses beta, but not always... depends on the other doping levels.

Latch-up. If your connection was an absolute necessity you could add an N-well ring around the device tied to +VDD.

However I smell that you are using some kind of array where you don't have the latitude afforded by a custom layout??

Well! You could hire me and I could sign an NDA ;-)

...Jim Thompson

I have used diodes from source AND drain tied to body:

Thank you for the advice. Right now the design is still in simulation stages so I cannot try this.

Thanks qq

W> QQ wrote...

I think there may be some freedom with the process. Why will an N-well ring tied to +vdd help? Is vdd meant to be the highest voltage on chip?

I can only afford free advice at the moment... :(

Thanks qq

Jim Thomps> >

Jim, thanks for your advice so far. This has been very useful to me. I guess I will have to do some more research before deciding what to do.

Thanks qq

Yes.

Lack of information makes it difficult to give cogent advice.

...Jim Thompson

Yes; be aware that a lateral NPN device can exist, where the substrate is the base. Also note that a transistor is still active with zero base-collector voltage, and still operational even with small forward B-C bias. And do not let the lousy beta (0.001 in some cases) fool you; just remember "total loop gain".