PLL Terminology Question

Software

...Jim Thompson

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| James E.Thompson, CTO                            |    mens     | 
| Analog Innovations, Inc.                         |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| Phoenix, Arizona  85048    Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
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Software

In _modern_ times. I've not heard that before and I'm wa-a-a-ay older than you. Analog phase detectors locked at 90°. Although you seem actually to be implying more loop gain?? ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     | 
| Analog Innovations, Inc.                         |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| Phoenix, Arizona  85048    Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Software

I am a fan of the D-flop bang-bang phase detector. It has, in theory, an infinite phase-error gain, which makes it interesting to analyze. That's the way to go if you want to lock an oscillator to an external input with picosecond long-term stability.

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John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

I get that backwards all the time, too. I don't know why.

Eric Jacobsen Anchor Hill Communications

Different loop types exhibit different error characteristics.

A Type-0 loop (no integrator) has position error. A Type-1 loop has no position error. A Type-2 loop has no position or velocity error. A Type-3 loop has no position, velocity, or acceleration error.

The references to error here refer to steady-state conditions.

Software

Yes, third order loops (or type III to salve Tim's wounded control-guy feelings) really use three integrators in the loop, on purpose. If you put a linear ramp into a control system like that, the DC error is zero. Of course it's as squirrelly as can be when it's coming into lock, which is why you need a bunch of analogue switches and so forth to make it work right.

Getting that right is such a pain, and so vulnerable to unforeseen circumstances, that it's far, far easier to estimate the ramp rate in software and put some small DC offset on the PD output to compensate.

Cheers

Phil Hobbs

Software

The metastability problem is for real, though. Many moons ago (actually in the same DBS system I mentioned in the H parameters thread) I used a 75S74 as a frequency mixer in an offset loop to generate the pilot tones for the satellite uplink. Even with very clean input signals, when I looked at the d-flop output on a spectrum analyzer, the peak looked like one of those old-fashioned drinking fountains that ran all the time--it wobbled and bounced all over, especially at low modulation frequency.

I'm really surprised that you can get good stability out of something that ugly. Or has the metastability issue somehow gone away since 1982?

Cheers

Phil Hobbs

Software

same DBS

mixer in an

very clean

peak looked

wobbled and

ugly. Or has the

I don't even remember 1982!

I used an EclipsLite flop as the bang-bang phase detector in the NIF timing system, differential ECL data and clock at 155.52 MHz, VCXO. Loop bandwidth was something like 10 KHz in search mode, 1 KHz operating, so if there was the occasional metastability, I didn't notice it. We got a couple of ps RMS jitter out of our whole box, so the PLL must have been better.

Holding 1 ps out of 6 ns, longterm, is asking a lot of the analog stability of any phase detector, and of the opamps and stuff downstream.

TTL logic, with symmetric master-slave flops, tends to dither a lot. Its metastability mode tends to be oscillatory, which essentially clips the positive-feedback loop gain and generally confuses the poor thing. ECL and CMOS gates are more likely to just resolve a little slower.

74LS74s could oscillate for tens of cycles if you teased them just right. Candidate for worst logic family ever, after RTL.

Gotta finish fixing the roof. The rainy season is almost here.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

Software

same DBS

mixer in an

very clean

peak looked

wobbled and

ugly. Or has the

A D-flop, by itself, is only good with a VCO that's constrained to less than 2:1 tuning range. Otherwise you can get harmonic locking... not necessarily bad, I've used it to advantage... see my patents. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     | 
| Analog Innovations, Inc.                         |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| Phoenix, Arizona  85048    Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

leave

Software

the same DBS

mixer in an

very clean

peak looked

wobbled and

ugly. Or has the

My application was a pilot tone generator that needed to make 70 +-

10/11 MHz pilot tones. (Don't ask me why, that's what the system engineers came up with.) Instead of using two synthesizers, I made 70 MHz from the 10 MHz system clock, then used a 74LS92 plus a couple of gates (or some such thing) to divide the 10 MHz by 11, and then used the two halves of a 74S74 to generate the pilot tones. Because the mixing was so ugly, I wound up using a couple of crystal oscillators locked 1:1 to the d-flop outputs. It eventually worked fine, but the extreme ugliness of the output spectrum from those d-flops has stayed with me!

Even if I'd used a nice diode-bridge mixer for the job, I'd probably still have needed the crystal oscillators, because the jitter spec was ridiculous.

Cheers

Phil Hobbs

,

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nd

ttdesign.com- Hide quoted text -

Interesting, what's the detector in a gyro? (I assume it was not an optical gyro.)

George H.

r e e

ttdesign.com- Hide quoted text -

OK Well I thought I was getting the type 'thing', but I'm confused again.

First what's type zero? I was thinking about a (type I?) loop with just gain control that I've used to lock a diode laser to the side of an absorption line. You've got to put a (single pole) lowpass between the error signal and the gain, or it's pretty much an oscillator.

George H.

,

ave

scottdesign.com

on

Well no picoseconds, but I've used the switched gain AD630 for phase sensitive lockins

George H.

.highlandtechnology.com  jlarkin at highlandtechnology dot com

Type 0 is a loop that has no naked integrators (a low-pass isn't considered a naked integrator in this context, as it has finite DC gain).

--
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My conservative friends think I'm a liberal kook. 
Why am I not happy that they have found common ground? 

Tim Wescott, Communications, Control, Circuits & Software 
http://www.wescottdesign.com

e

ttdesign.com- Hide quoted text -

Hmmm OK, For the diode laser locking thing, the piezo (plant) has a resonance a bit above 3kHz. Say I use a low pass filter with a 1 second time constant, and then crank up the gain til it's just below the oscillation point.... how 'naked' does the integrator need to be? (would 10 seconds and more gain count?)

George H.

Software

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Speaking of which, while I have it fresh on me mind, I've been wondering how one of those cheap laser diodes would behave in PV or PR mode and would they survive another laser of equal type pointed into them?

Just thinking out loud here. I have a few I can test that with..

Jamie

Software

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If you put in a notch filter, you can get the loop BW a lot closer to the piezo resonance, like 0.3 f_0 vs 0.03 f_0.

Cheers

Phil Hobbs

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Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 USA 
+1 845 480 2058 

hobbs at electrooptical dot net 
http://electrooptical.net

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scottdesign.com-Hide quoted text -

t -

Grin, OK I'm not saying that a single pole low pass and then gain, is in any way optimal. But it works... is it type 0 or type I?

(Does notching out the piezo resonace work? I've never tried that.)

George H.

Software

quoted text -

Notching works great, if the resonator Q is high. The notch filter's phase shift goes away on the scale of its bandwidth rather than its centre frequency, so it has almost no effect beyond a few times delta-f.

In my atomic force microscope days, I used that trick to get a factor of

10 in loop bandwidth with a piezo bimorph whose Q was right around 30.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 USA 
+1 845 480 2058 

hobbs at electrooptical dot net 
http://electrooptical.net