I have just started reading about PLLs. Most of the (introductory) material I have seen always starts with the phase as the detected variable. And phase = Integral(freq). But why not use frequency itself? That is, why cant you determine the frequency (using a counter) and compare that with the desired frequency and thus generate an appropriate error signal to the VCO?
Thanks,
vkj
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In fact, this is a general control loop theorem -- anywhere you have a variable under control, you can achieve zero steady-state error (at constant output) with an ideal integrator. Or for an infinite ramp input, you need a double integrator, etc.
In practical terms, you use an op-amp for these sorts of control problems, which approximates an integrator, but still has finite DC gain (60~120dB depending), resulting in a nonzero steady state error term.
Only true integrators, usually physically realized manifestations of mathematical quantities, like phase to frequency, or position to velocity, are capable of achieving zero steady state error.
Fundamentally, this is why time can be measured so damned accurately -- you can count the vibrations of individual atoms in an atomic clock and keep your circuit in perfect lock-step (and, in turn, radio transmitters, world power distribution networks and internet-sychronized clocks). Even if it varies in the short term (a phase shift), the frequency (rate, ticks/second) remains exactly constant.
Tim
--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Usually a PLL is used to generate a frequency that is an integer = multiple of=20 the fundamental, sometimes as much as 1000 times. For instance, to = measure a=20 low frequency, such as 60 Hz, to a precision of 0.001 Hz, you have the = PLL=20 generate a frequency of about 60 kHz, and then divide that down with = three=20 decade counters to 60 Hz. When the two are compared, a very small change = in=20 frequency will cause a phase error, to which the loop can respond.
Of course, these days it is also fairly easy to measure the period of = the 60=20 Hz signal to a high degree of accuracy with, say, a 10 MHz counter, = which=20 will give 166667 counts, and this can be inverted and converted to = frequency=20 to a resolution of 6 uSec. But when I was working with them in 1980, = such=20 computation was rather difficult and expensive. I had actually worked = out a=20 design which would enter the count into a calculator which would do the=20 floating point math and display the result.
Now a very popular use of a PLL is to generate higher internal clock = signals=20 on a PIC. The PIC18F2450 uses a 20 MHz clock to generate 48 MHz for full =
speed USB. So the oscillator is divided by 5 (4 MHz) and then multiplied = by=20
12 using a PLL.
I found a lab document that describes some of the concepts, and it uses = the=20 very popular 74HC4046 (or CD4046) PLL:
In addition to the desirability of using phase error (which is really only true once the loop is locked -- before then it's a pain in the behind), it's easier to make a good accurate phase comparator than it is to take accurate frequency measurements.
So: less hardware, more desirable results -- what more could you want?
--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?
Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
if you want to determine the frequency with a counter, you need some time to count a result with enough precision. When working with low frequencies, you need 1 second, 10 seconds or even 100 seconds. The long time needed is very bad for a control loop to adjust the frequency of the oscillator. A phase detector is faster and needs less parts or transistors.
When working with low frequencies, it is better to count the period time.
You never answered (or I missed) if you said what _type_ of phase detector you are using. At very narrow bandwidths a PFD with lots of "ooomph" could be the problem... bouncing source, PFD knocks VCO too far. ...Jim Thompson
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I love to cook with wine. Sometimes I even put it in the food.
You can but you're doing to get a wandering VCO with in a
+/- 1 cycle for the correction. That is, if you are dealing with a 1:1 ratio lock.
If the VCO was being scaled to produce a multiple of a stable frequency, then your wandering effects will be multiplied also, simply due to the fact that more cycles are going to be in error before error detector will notice 1 cycle +/- from the scaler.
Yes, a phase detection is needed, even if you use a frequency count method to ensure this does not happen.
Depending on the required design, will dictate the gain needed in the error detect circuit and phase shift offset needed incase exact phase alignment is needed.
It would be like designing a good working PID loop.
Well, on the bright side, no one else seems to have a clue either :).
After a bit more reading, heres my take: Phase detection is used because its FASTER, since d(phi)/dt = frequency. The analysis of PLL feedback in the "s" domain deals with "s" as the modulation frequency. not reference frequency, meaning the dynamic response to change in frequency.
I still think it makes sense to use frequency as the feedback parameter when you are only interested in holding the frequency constant in steady state, as in an oscillator circuit. Heres the setup: a PIC generates a dc voltage that controls the VCO. The VCO output is counted by the PIC to determine the frequency. The error in the count is the feedback parameter and you can use your usual digital controller techniques to suitably generate the dc input to the VCO, completing the (digital) loop. You only need to design for zero SS error. This is certainly simpler than the usual set up with ref. oscillator, programmable divider, and the feedback filter netowrk. Of course in my setup, the PIC osc is the freq. reference.
A simple example: An oscillator whose output is f=1000+n, n=0..1000. In the conventional setup you would need a reference freq of 1Hz. possibly derived from a 32Khz xtal and divider. You would also need a prog. divider
1000(1)..2000. PFD loop filter design is done in the analog domain. Instead, all of this can be doen inside a PIC implementing a digital controller. As a bonus, you can also display the frequency for free. Doubtless the response time will be slower (prob. by about an order of magnitde) but if all you are interested in is steady state and you can wait for perhaps a few 100 miliseconds, the PIC version is quite the way to go, IMHO.
Thanks for the responses.
vkj
--------------------------------------- Posted through
Yeah, and that era was now. I find it hard to believe that, in this day and age, kids are still being taught Routh-Hurwitz and root locus. On paper. By hand. I learned them for one test, and summarily forgot them!
Tim
--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Routh-Hurwitz testing is used as the basis for at least one robust control scheme.
And I end up sketching root-locus plots all the time when I'm doing control system design; sometimes I even put them up on Scilab and look to see what it says about them. I wouldn't say that doing them by hand is essential -- but understanding what one says is, and the best way to do that is to learn to do at least the basic ones by hand.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
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