PLL ICs with analog multiplier phase detectors ? Are they still around ?

Both are almost free, but the FPGA needs to be programmed.

The multiply-and-average approach is guaranteed to work, though, and fitting isn’t.

Because fitting emphasizes the worst outliers, it falls apart completely at low SNR, whereas multiply+average works even with SNRs way below 0 dB.

Yes, well, I guess we'll have to come up with different terminology for CPLDs (SuperFPGAs) and actual FPGAs (UberFPGAs).

The Greenpak devices are a long way from an FPGA, by any measure. I was hoping to use one on my current design as a "sweep" to include multiple bits of level converters and amplifiers and power regulators. Turns out while these three functions are available in their devices, no device includes even two. I was particularly disappointed that the logic level converters were not at all widely supported. I did manage to find a regulator device with simple logic functions. A significant disappointment from what I had hoped to do.

So, no, I am not remotely inclined to refer to them as any sort of FPGA. They are much more like a bit of this and that, snips and snails and puppy dog tails.

I believe Renesas is working on an actual FPGA-like device which has been in the announcement stage for some time now. Just the other day I saw that they still do not have even a preliminary data sheet as they wish to continue to "perfect" the design.

Oh, well.

True in general, but with a power source, wideband random noise isn't usually the problem, it's waveform distortion due to the generator design, plus power-system transients.

Which is why in practice one does some data grooming first, like impulse clamping or blanking, if the impulses are common enough to matter.

I would assume that a distorted waveform may also affect the imputed zero crossing locations from multiply-and-average, at least the odd harmonics will, but I don't know how important that is for the OP's intended use. Probably will want to clamp the transients as well.

Joe Gwinn

Nope. Multiply and average pulls out the in-phase fundamental component to any accuracy you like (and that your digitizer can manage), while ignoring all the harmonics to the same accuracy.

There are the usual Shannonish tradeoffs between accurate tracking of FM and noise elimination, but you can notch out the harmonics by simply averaging for an integer number of cycles.

Having the correct phase vs time, the same numerical oscillator code will make a clean replica shifted by 90 degrees so as to match the fundamental component of the input.

I should say that if one is trying to lock to an edge, rather than to the fundamental component, life does get harder and less well defined as the SNR drops or the waveform gets gnarlier-looking, as you say.

Yes. And doesn't the multiply-and-average approach implicitly depend on the full-bandwidth waveform being symmetric in time? Said another way, would the zero-crossings of a asymmetric triangle wave be precisely located in time?

Joe Gwinn

The theorems are correct, so the phase of the fundamental can be located to any accuracy you like, regardless of the waveform symmetry or lack of it.

Identifying phase with the position of the zero crossings becomes an ill-defined operation very quickly as the SNR declines.

Even a DC offset will screw that up.

Which theorems?

Yes.

What we need to know is what matters most in the OPs problem.

Joe Gwinn

Fourier decomposition. You derive each Fourier coefficient as the normalized overlap integral of the corresponding eigenfunction and the given function. The computation becomes exact as the limits of integration go to infinity.

Cheers

Phil Hobbs

Some great ideas !

My route would now be to use an inexpensive-ish ARM Cortex-M0+ most likely. Running balls out should maybe give me two PLLs even. For $1

Don't need a sine-wave output. That is provided from another place. Just need a rising or falling edge to indicate phase sync is all.

I will also have to look into what Phil was talking about.

I originally was wondering where they all are now but yes, a micro these days can do it all and even more.

Maybe I also kind of miss the days of the old PLLs that were around.

OK, more posts below to read.

You're all right on here ! Thanks !

boB

This application is for an inverter synchronizing to grid.

We are doing this now in software both ways. Zero crossing detect and multiplier/filtering PLL. The zero-cross method works but can be a but jumpy once in a while. The more complicated method works better I think but takes a lot of processor time. It CAN also become somewhat unstable if not given the right coefficient values etc.

Since it can be computationally intensive so I was trying to see if there might be an out of the main microcontroller's code space metod of accomplishing this part, inexpensiviely. Another micro, although a cheap micro can do this instead of an old style PLL IC.

DC offset should not be a problem. If there is DC on the grid or generator, then the whole unit should disconnect from that AC source.

Appreciate the extra brain power from you guys.

boB

Programming these guys is easy enough. You can even re-program in circuit, or, upload new circuit to its RAM via I2C if you want.

I would love it if they had one of these GPs with just gates and flip-flops and LUTs.

We use these and they work great ! We could also replace an old Xylinx CPLD with one if it tends to go EOL.

boB

Thanks. That part number did cross my mind.

I think that a cheap ARM like JL mentioned is the way to go here.

boB

If you tweak it wrong, it'll lose lock, for sure. The loop can also oscillate while remaining in lock (more or less).

A reliable way of doing the lock detection is to do the multiplication with both the sine and cosine components of the reference. The loop will lock at quadrature, where the other multiplication reaches a peak.

Multiply-and-average is much better than a phase-frequency detector. PFDs are sensitive to the number of edges, so any time you get a spurious edge, the loop loses lock and has to reacquire. Multiplying phase detectors and even XOR gates are much better if the signals aren't squeaky-clean. An XOR doesn't care about transitions, just the duty cycle of the result.

To save processor time, you could use a simple IIR filter to knock down the harmonics a bit, and then multiply by +-1, giving the rough equivalent of an OR phase detector with lock detection. If you pick the coefficients cleverly, you can do it all with a few shifts and adds.

(You want to avoid thresholding the filtered signal before XORing--otherwise junk happening near the zero crossing will get amplified a lot.)

(The RF PLL chips weren't that great either.)

Cheers

Phil Hobbs

The inverter providing power to that grid, where the provided power comes from a windmill or photovoltaic source?

How distorted is the grid power waveform? How symmetric in time? My recollection is that the waveforms can be pretty banged-up, largely due to the non-linearity of transformers and the fact that it takes a log of engineering to get rotating generators to provide good sine waves.

What is the metric we are trying to minimize? In other words, what constitutes perfect synchronization?

I recall the old manual method used in power plants, an incandescent lamp connected between the grid (a bunch of other generators flying in formation) and the new candidate to fly with that flock - the metric was when the lamp went dark. One bounced between advance and retard, and split the difference. When the switch was closed, there would be a transient while the flock forced the candidate to fly right.

In modern terms, how big a sync transient is permitted?

Yes. Zero-crossing detectors are always jumpy in real-world applications. Avoid them if possible. Batch methods are usually far better behaved.

Yes.

This ought to be workable - modern micros are cheap and powerful.

Sounds right.

Thanks. It is an interesting and practical problem.

Joe Gwinn

It wouldn't take much of a uP to make a software quadrature DDS and do a multiply against the digitized line waveform and use the product to servo the DDS phase or frequency. Do that calc at some modest number of KHz. It averages, so ignores noise and harmonics that would wobble a zero-cross detector.

One could do a true phase - not frequency - locked loop too.

Another idea: make a software bandpass filter but turn it into an oscillator when the line voltage fails. Just for fun; the DDS makes more sense.

Or use a uP internal timer (most have them) and sync it with the line frequency, and free-run when the line fails. That could be really easy.

Agreed, if it’s a new design. Even a Cortex M0+ has a single-cycle 32x32 multiplier.

Yup. Extra credit for picking a sampling frequency that won’t alias nearby harmonics down inside the loop bandwidth.

Yes, it’s PLLs that are in view—a frequency-locked loop wouldn’t do it.

Cheers

Phil Hobbs

Why screw with an MCU when you can do this easily in an FPGA? Even a small FPGA is more than adequate to implement all the functions for this. Efinix parts are very inexpensive and they now have a 100 pin QFP so you don't need to screw around with BGAs.

You don't say what resolution you need in the ADC, but you can use differential inputs to create a sigma-delta like converter that will give you 12 bits without trouble. So, no external ADC.

One big advantage of FPGAs is no need for trying to make a single processor look like multiple processors, with all the attendant issues you have to deal with.