PLL ICs with analog multiplier phase detectors ? Are they still around ?

You could make one. Use a dual comparator and an xor gate for the multiplier.

Or a quad XOR gate to be really cheap.

All the analog AM/FM radio chips are gone. You can still get the MC1496, which is sort of a DIY version.

Using the SLG46537 mixed-signal PLC or similar you can build a pair of nice edge detectors with its four onboard comparators maybe sort of like this:

And then with the 8 stage async state machine you can implement several phase detector topologies, once you've got edges for firing the transitions.

I think 25 cents or so in small quantity:

Er meant to say "zero-crossing detectors" there, rather.

Yes, you can make a nice phase-frequency detector in an FPGA.

Thanks for the suggestions.

We do already use the Silego Greenpak devices. Great parts !

This question was intended to find one like the old PLL chips that, Like Phil Hobbs said, are all gone now. As fo the MC1496, we used to actually use those many decades ago in an FM tuner we used to make.

The reason for the analog multiplier instead of digital comparator or zero crossing detector is that this was going to be used for synching to 60Hz (ish) AC grid or generator sine-waves that may very well be distorted. Especially genny waveforms. Those do not ensure that zero crossing is clean and detectble repeatably.

I had even looked to try and find an analog multiplier IC and those are not availabe for cheap. Could make one out of log amps using CD3046 transistor arrays but that is quite a few parts.

I think that the way to do this may actually be to use a cheap ARM Cortex M0+ or similar micro with at least 2 A/D inputs and at least some speed. 60 Hz area should work easily done with a 48 MHz part I think. The whole PLL should be able to be done in one of these actually. Digital filtering and all.

Thanks for all of the input.

boB

I think feature-rich mixed-signal FPGAs that are around the quad XOR gate price point are pretty exciting!

At 60 Hz you can do a nice all-software PLL. Lots of cheap ARM processors include plenty-good-enough ADCs and nice timers.

He wants an analog multiplier chip. so he can multiply by a local sine wave. The XOR gate multiplies by a local square wave - cheaper, but not the same, Think about the higher odd harmonic content.

Just for reference here are a couple of inexpensive analog multipliers, not high performance but kind of neat circuits:

This one uses Cds cells so probably mostly historical interest:

It's just Jim Thompson's crude analog multilpier, stripped of the linearity improving bits he put into the MC1495, which slowed it down a bit

He did rip off Barrie Gilbert's original idea, to produce a crude cheap mass market device.

FPGAs at TTL logic prices? Has TTL gone up sharply in the last year or so? Which FPGAs would this be?

Or was this sarcasm? Text medium often requires some explicit indication of sarcasm.

On 2023-05-28 00:52, boB wrote:> On Sat, 27 May 2023 21:10:34 -0700, John Larkin > snipped-for-privacy@highlandSNIPMEtechnology.com wrote: >

If the waveform can be really gnarly, then what you want is a digital lock-in, where you multiply samples of the input by samples of a good-quality sine wave, and relying on the orthogonality of sines and cosines in both the continuous-time and sampled domains.

There are various way of doing that, mostly depending on whether the sampling clock is derived from a fixed-frequency oscillator or from one locked to the input. There are advantages to both.

Using a fixed-frequency sampling clock is simpler, and all the nice Fourier transform and DSP theorems hold exactly.

Using a phase-locked sampling clock helps keep all the sampling and slewing transients fixed, so that non-ideal behavior of the sampling system doesn't lead to phase modulation. (Frequency-domain applications are absolutely brutal at showing up any non-ideal behavior of your sampling system, which is why everybody seems to screw up their first digital lock-in design.)

We're obviously relying on the validity of the orthogonality relations in both cases, so in the variable-clock case, the tuning range has to be kept within reasonable bounds. (The math isn't difficult, but you do have to take some care.)

Cheers

Phil Hobbs

The problem here is (as usual) poorly defined. I think Bob wants to generate a sine that's sync'd to the 60 Hz line, so the pull range will be tiny.

One could software generate a DDS sine, conveniently available in quadrature, and multiply the 90 degree guy against the acquired reference sine to make the loop error, which servoes the DDS frequency. Something like that.

Software DDS, filtering, PLLs, things like that are fun. One can Spice and tune a whole analog system and then just code it in the most barbaric way.

Multipling a signal times a square wave is really easy. Just switch an amp between gain +1 and -1.

An analog multiplier and and analog sine wave can work just as well.

Getting tunable clean sinewave oscillator for a phase-locked loop can be tricky. I've worked out a couple of ways of doing it, but haven't put any of them into practice.

A well filtered Direct Digital Synthesis chip can come pretty close

There's also a lot of high frequency digital hash floating around the powers, and it takes careful design and layout to keep it out of the places where it creates problems. Using ECL logic puts much less hash on the power rails, but that tends to be impractical.

Getting the layout and right and keeping the high frequency hash away from the sensitive bits takes no less care.

Of course the square wave has all the odd harmonics up to the limit set by your switching speed, so that ease comes at a cost.

Sometime a "modified sine wave" which is to say a three level waveform which is high for 2/6 of the period, zero for 1/6th of the period, low for 2/6th of the period and zero again for the last 1/6th of the period, can be handy - it has no third harmonic content and the fifth and seventh harmonics are reduced.

Some call a chip like the SLG46537 a "micro-FPGA", or a mixed-signal CPLD with FPGA-like features, or whatever u wanna call it.

The analog multiplier function in figure 24 here

only requires half a LM13700, and some resistors.