the output of the the counter is fed to the 2nd input of the phase comparator (in order to acheive the lock) and the desired multiplied frequency (i.e the input to the divder) becomes a locked stable output. (put in simple terms)
Chris
You've got a 1MHz crystal oscillator, the "reference frequency". Feed that into a phase detector. You've got a wide range voltage controlled oscillator, going from 2MHz to 20MHz. You put your divider between that oscillator and the other input of the phase detector.
The phase detector will always output voltages to try to get that second input to match the reference oscillator, though of course it may not always lock. In the example, the VCO can never equal the reference frequency. But if you set the divider to divide by 2, the phase detector will see a 1MHz signal if the VCO is set to 2MHz. The phase detector can then output the signal to steer the VCO to exactly 2MHz, so both inputs to the phase detector are equal (and in this case equal to 1MHz).
Move the divider to divide by three. The output from the phase detector gets starts moving the VCO, and when the VCO hits 3MHz, again the two inputs to the phase detector are equal.
And so on.
In effect you have a multiplier. The output of the PLL is the reference frequency multiplied by the division factor in the variable divider chain between the VCO ouput and the phase detector input.
Note one could get the very same effect if one started with the same reference frequency and then had a bunch of multipliers. Indeed, that was what was common before semiconductors made PLL synthesizers practical for everyday use. But multipliers are much bulkier than digital dividers, require a lot of tuned circuits, and if you're not careful you can end up with plenty of spurious signals.
Michael
I'm not very understand how does the divide by n counter work? Thank you
thx mike...but one more question... the ref frequency would not be changed, it's always 1MHz, and i placed a divded by n counter(*10) between vco and phase detector, therefore the 2nd input of phase detector would be 10MHz, but the ref frequency still 1MHz. The question, what is the result after detection? why the output the 10MHz? why not 1MHz?
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