PID question

On 22/11/2006 the venerable Jim Thompson etched in runes:

. .

Actually, a "Pole" is someone native to Poland. A "pole" is a linear measure of one-quarter of a chain or five-and-one-half imperial yards.

;-)

Just to add a few thoughts. If your A/D can sample at 100k samples per second, you'll have 10us sampling time (assuming no s/w overhead). You must also take into account that, since you have a discrete-time closed-loop system, you must allocate several samples to your desired response time, so as not to de-stabilise the loop. That will slow it down, but may still be acceptable for what you want to do. My very rough guess would be a response (settling) time of at least 100us, probably a lot more (for a very stable loop).

If/when you have the circuit and PIC code working, please post the current limiter speed of response you get to a load step change.

Yes, thank you! I wasn't sure if I was describing this clearly. This is exactly what I'm doing. No analog current limiter here. On your next post where you say that "you must allocate several samples to your desired response time", do you mean that I should be taking an average of several samples before feeding it into the PID loop? I am doing this, and yes it probably would be very unstable otherwise. I will post results when I get something more finalized, which could take awhile.

What I meant was that you should tune your PID so that the speed of response of the current limiter is such that there are several samples spread along the transition curve (say, at least 10). Otherwise your system may exhibit oscillations around the set point in the transient period (under-damped) and may be dangerously close to instability. Given that a bench PSU is supposed to drive a variety of loads, I would prefer to tune for a conservative (over-damped) response at the expense of speed.

The averaging that you're doing to obtain each sample is a low-pass filter that removes glitches and noise. It's a good thing. But I was talking about the samples that the PID sees (after the averaging). So, if each sample is the average of, say, 5 A/D readings, this would result in a loop sample time of 50us. This is the sample time I was talking about. So, 10 samples in the transient period of the closed-loop response would result in a response time of around 500us.

To tune your PID, start with P only (adjust it to a conservative value) and then slowly increase I until you get a suitable response (remember, slow is usually better in terms of stability). Then play with P and I to fine-tune. You may not need the D term as it amplifies the noise present in the error term.

Then he is in trouble. Even if he can sample the current measurement with his ADC 100k times per second, and cycle his PID algorithm for each sample, the gain bandwidth product of the resultant current limit will be something on the order of 5 kHz. An analog PID current regulator based on a jelly bean opamp, like an LM324, would beat that by a mile.

Yes. Thank you. We have been talking past each other, I guess. I thought I explained to him that the current regulating loop had to be fast, without emphasizing enough that his digital system is not fast enough for much of a current control.

snipped-for-privacy@yahoo.com wrote: (snip)

(snip)

Not at all what I think he meant.

Each sample you take must be used as quickly as possible, to minimize time delay inside your control loop.

I think what he meant was that it takes many cycles of your sample and control algorithm to restore the system to setpoint, after a disturbance, so just because you can sample and cycle your program 100k times per second, don't expect to recover, completely, from a step current error much faster than 10 to 100 sample times (100us to 1000 us), especially with load impedances other than for what the control loop tuning was optimized.

I agree. That was also my suggestion on another thread, but I guess his demands for speed are not high and he's decided to do it digitally... I would definitely go for the op-amp design, no question about it.

Yes, that's exactly what I meant.

It would be interesting to see what kind of speed can be achieved with the discrete-time loop. If/when the OP completes the project, perhaps he could post some results.

On a sunny day (Thu, 23 Nov 2006 11:17:16 -0500) it happened John Popelish wrote in :

Question: I am a bit confused here, this comes from my experiments with fast digital PLL locking, say all is normal, no current limit active. Then he connects some load (let's say R only) and the sampled current point at t0 reads 1A. Because it is digital he KNOWS (from the DAC) the voltage. Say the voltage was 10V. He now can calculate he has a 10 Ohm impedance, and this calculation is available at t1 (few micro seconds later).

If the current limit setpoint was 100mA, he then sets the DAC at t2 to an output voltage of 1V. The next sample read at t3 will be 100mA and balance will have occured.

With inductive or capacitve load you will get no balance that quick of course. But the basic calculation should converge fast (An ideal L on output would lead to 0V (divide by zero error ;-) ), an ideal C on output would lead to

This is not exactly PID is it? Is this correct?

Yes, that is not PID.

John Popelish wrote:

The digital current limiting was sort of a long shot, a chance to eliminate the entire negative power supply and free up one of my two DAC outputs.

Previously, I was working on a design that used a DAC out for the voltage setpoint, and the other DAC out for the current setpoint. Each of these functions was then fully realized with op-amps. I'm also using a switching pre-regulator, and this needs a way to track the output voltage, plus one or two volts. I thought it would be great to use the freed up DAC to set the pre-reg output. Here's roughly what the circuit design looks like (copy into Notepad to view): ___ .-----|___|------------. | | | || | o-------||--. from | | || | pre-reg | .--------------------------o | | | | |\\| .--' | | | '--|-\\ | ___ |/ | .-. ___ | >--o--|___|--| | | | Voltage DAC -|___|---o-|+/ |> | | | | |/| | | '-' | .--' | | | | | | V .------o----' === |\\| - | | |+ GND '--------------|-\\ | | .-. === | | >--o | | | /-\\ | Current DAC -|+/ | | | | | | |/| | | '-' | | || | | | .--' o------||------------' /| | '--o-o----+ | || ___ /+|---' | out '----------|___|--------< | | \\-|-------' .---- - \\| | instrumentation amp, | for current sensing === GND (created by AACircuit v1.28.6 beta 04/19/05

The output pass transistor is a Darlington. The output goes into a low pass filter, then into another op-amp configured to adjust the output voltage of a National Simple-Switcher. Is there anything to watch out for with this design? It seems to work fine. I have a dual polarity supply to the op-amps. In this configuration, all the micro does is sets the output of the two DACs and drives a user interface. I'm still going to spend a little more time on the all-digital current limiting, but I suspect it won't be responsive enough.

Well, we have certainly discussed a number of variations from this approach for you to think about.

What I don't like about this approach is that the voltage regulator is the slave to the current, rather that what we have been discussing as a cascade. I think that is suboptimal.

Also, the voltage control is proportional, with a high frequency roll off, not PI or PID. The current controller is a PI controller (integral only for the lower opamp in series with the proportional effect of the upper opamp, but including both opamps in that loop lowers its high frequency performance.

I guess you would have to build and optimize (or simulate and optimize) some of the versions we have been discussing, to prove that they can actually work better than this.

Since the upstream switcher is a lot slower than this stage, have you thought about doing the entire switching controller in software?

Now I'm understanding what you were suggesting way back. It sounds like it is essentially swapping the current and voltage controllers, along with the addition of this low selector. I was thinking something like this (paste to Notepad to view):

|| to current sense .---||---. | | || | | || | | o-------||--. | |\\| | | || | voltage output feedback -|-\\ | | |\\| | | | >---| '---|-\\ | |/ .----|+/ | | >----o-----| | |/| '---| | | |/| | | | V setpoint .-|----| | | | .--o output |\\| | | | .---------|-\\ | | | | | >----|

Almost but not quite. Tie the VEA output directly to the CEA. You know the sensitivity of the CEA so all you have to do is implement a local clamp around the VEA so it cannot demand more than the current setpoint.

Yes, it's one of those things that gets used repeatedly because everbody copies it. As you say it has problems with amplifiers going into and coming out of saturation.

DNA

Genome wrote: h the diode voltage drop, and needs a

Is there a standard way of doing this? I can think of some, but none seem to be very elegant. I'm trying to not require another op-amp. I have 2 more which are being used elsewhere.

Yes, current changes faster than voltage, if there is a bit of capacitance between the pass device and the current sense.

Yes, if you want quick recovery each time you change over from voltage control to current control, or vice versa, you have to prepare the not operating controller so that it arrives at the existing output, given the existing error, just as the trade off occurs. This is easier in software, where you can start with the output and back calculate the value of the integral term that makes the produces the given output, right when the switch from current to voltage control occurs.

Unfortunately if you want precision/performance then you are forced to use an op-amp. In this sort of application you don't necessarily need amazing performance. An LM324 will do the job for you.

Your ideas might not seem elegant but the chances are they will work. Have a look at

For something that 'might' do what you want with a single quad op-amp.

DNA

I'm just wondering how well it'll maintain voltage regulation with little or no load, with a DAC output step of 1mV. Maybe this is where the output filter cap comes into play.

Thanks for the schematic. I still need to determine if I'm going all analog, or hybrid (analog current control/digital voltage control).