Phase Margin Question for Phase Locked Loops

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That's fine. Still, you don't understand why. An inverter between the error signal and the loop is necessary to achieve negative feedback. The inverter provides 180 degrees and the integrator by itself eats half of that, leaving 90 degrees phase margin, the best one can do. Other roll-offs decrease the phase margin even more, putting some ringing into the response. 40 degrees of phase margin usually allows a very acceptable overall response.

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That's easily changed without altering their characteristics. All feedback circuits need inversion to be stable. It's the additional phase shift between DC and the zero-dB frequency that matters.

Jerry

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Engineering is the art of making what you want from things you can get.
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I most certainly do. See Barkhausen in my original post.

An inverter between the

The

of

Well, we have two integrators in this case, the op-amp with capacitive feedback and the VCO.

Slick

We would like to improve the current design, if we could. But it certainly already works. We would like to omit some fast acquisition

1N4148 back-to-back diodes that we have in parallel to the output resistor, as they supposedly distort our audio modulation at low freq. However, the lock-up time is slower without them, so we'd like to adjust the poles and zeros for faster lock without them, without losing too much phase margin/stability.

then

VCO

phase

Well, that was my orginal question, do all phase detectors, whether XOR or phase/freq, have the 180 degree phase shift that you need. Apparently, yes.

Slick

actually

so,

Most of the literature uses G(s) for the forward gain and H(s) for the feedback path.

But, to each their own.

recently

do

What sort of phase margin did you shoot for? And what type of filter did you use?

Slick

Yes. I forgot the N. I was thinking of a loop I did with N=1. I actually prefer to use G(s) for open-loop gain and H(s) for closed loop gain; so, personally, I would write it as:

G(s) = kPD * A*(s+B)/s * kVCO/s * 1/N

You say in another post that you want to improve the lock time. I recently designed a loop that had to lock very quickly. I found it useful to do Bode plots and step response using SCILAB.