Phase detector with a MC1496

You turn the lead-lag loop amp into an integrator/Schmitt trigger oscillator that sweeps the VCO back and forth slowly (dF/dt << f_0**2), where F is the oscillator frequency and f is the loop frequency domain coordinate.

The Schmitt output has just enough amplitude to overcome the worst-case offsets. (There’s a way to connect it to avoid jumps in the loop amp output when the Schmitt changes state.)

Once the loop comes into range, it jumps into lock and stays there, because the negative feedback dominates.

If the resulting few millivolts is a worry because of AM-PM conversion, you can short the Schmitt output to ground when lock is detected.

Cheers

Phil Hobbs

Four resistors. ;)

The two integrators aren't really a problem, but granted, it does take a bit more work to make the loop stable. The loop becomes conditionally stable, i.e, the loop gain required for stability has an upper bound as well as a lower bound. The reward is that the phase error in the locked state tends to zero.

Basically a FF with edge-sensitive set and reset inputs, I guess?

The PLL I use in CERN's Proton Synchrotron beam trajectory measurement has a PIDD regulator. It follows the beam around the machine all the way from injection, through acceleration, up to ejection. I didn't need a phase-frequency detector, because the frequency is initialized to the right value to a relative error of ~1e-4 or so a few milliseconds before beam injection and the initial phase is then aligned with the accelerating RF. It's locked by injection time and then stays locked to the beam for the remainder of the cycle.

The phase had better be right, or I'd miss the particle bunches. That's why I wanted the extra integrator.

Jeroen Belleman

I've got lots, but no circuit diagrams for them, and anyway nobody sane is going to share circuits with you.

I've got lots, but no circuit diagrams for them, and anyway nobody sane is going to share circuits with you.

Only if the edge is in the right place. Edges get moved by Johnson noise, and a knife edge response implies a very high bandwidth, which includes the very high frequency components of the Johnson noise.

From a jitter point of view, multiplier style phase detectors average out a lot of that very high frequency noise, and deliver lower jitter.

But it happens to be wrong. It won't be the first time that the marketing department has screwed up a data sheet.

The more detailed description shows it to be a pair of current sources with just one of the current sources turned on for shorter and shorter times as the loop approaches lock. The trick in the 9046 is that both them end up turned on for not much more than 15nsec when circuit is just about locked, while the equivalent phase detector in the 4046 generates no correction signal when the system is very close to lock.

AI is known to hallucinate.

Since you clearly didn't understand what you were doing, this isn't all that surprising. The jitter comes from having no feedback signal when the circuit is very close to lock, and you don't seem to have understood that.

And I'm no fan if the PD2 phase detector, or PD1 either. PD2 is great for getting a circuit close to lock, but when you have got close to lock you should switch to a four-quadrant multiplier phase detector because it is appreciably less noisy - giving less jitter on the phase-locked output.

Have you posted the schematic somewhere?

There will be some phase shift in the bottom transistors. It might be less if you drive the emitters (pins 2 and 3) ideally from a square wave via resistors, and hold pins 4 and 8 at the same constant voltage to use the bottom transistors just as cascodes.

The upper transistors won't need much voltage swing on the bases to fully switch them, but a square wave will work better. If you can feed them a 200mV square wave I expect that might be best.

(Reading on my phone, so I saw this. )

Faster is better in this case, like wideband FM.

The Johnson noise amplitude goes as sqrt(f), whereas the slope of the edge goes as f.

That means the Johnson noise jitter goes as 1/sqrt(f).

The faster edges also reduce the effect of low frequency noise.

Cheers

Phil Hobbs

There's no doubt that you get less jitter with a faster clock, but for a given frequency, detecting where the sine waves are over the whole of the waveform with a multiplier style phase detector delivers a less noisy estimate of where the phase is than you can get out of a switching edge detector, which looks only at the zero-crossings.

That detected output is fed into your voltage controlled oscillator, and more noise on that estimate of the phase means more jitter on the output of the voltage controlled oscillator.

John’s thing had nary a sine wave in it. Wide bandwidth helps the clock jitter, but a sine wave doesn’t get sharper if you widen the bandwidth on that input.

Cheers

Phil Hobbs

Our input was a fiberoptic signal from the master timing system, biphase data at the OC3 rate, 155.52 Mbps.

One big upside of our architecture is that the important stuff - photoreceiver, VCXO, and the dflop phase detector - is differential ECL, which is crazy fast and almost totally immune to power supply noise. Low tempco compared to cmos too.

I'm going to run an experiment this week to characterize an Efinix T20 FPGA for various prop delays and jitter. We built in a bunch of 32-bit pseudorandom shift registers in various places on the chip, and I can turn them on and off and see how they crosstalk into a few critical paths. I don't expect delay stability or jitter or tempco anything like ECL. FPGAs that I've tested have prop delays that are crazy sensitive to core voltage, with lots of ground bounce.

This proto board also has my el-cheapo DDS clock generator and a triggered-oscillator digital delay generator. Triggered oscillators seem to be an endeless habit. Better than crack cocaine I guess.

We threw in a snap-apart test board for the STSPIN958 h-bridge thing. The chip is great but their eval board is awful.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Of course it did. A square wave is just a sine wave plus all it's odd harmonics up to a limit set by the edge speed.In reality a square wave is a trapezium wave, and each edge has a finite slope.

A multiplying detector allows you exploit the width of the transition over the period of the transition, and that squeezes out an appreciable amount of very high frequency noise.

It lets you reduce the bandwidth of the phase estimate you extract, which is a relatively low frequency signal - not in absolute terms, but the useful part of its frequency content is obviously below the frequency you are generating and controlling.

A more or less linear multiplying detector also introduces less non-linearity into the process of extracting the phase difference information from the two waveforms being compared, and that's noise too.

All digital is analogue when you push it to the limit, and analogue engineers do better with ECL than digital engineers who have spent too long with an over-simplified idea of what they are doing.

I once had an entertaining conversation with a (rather good) digital engineer who claimed that ECL hadn't delivered what it promised on the jobs he'd been involved with. When I responded that it had worked for me when I'd used it, his response was that I was an analogue engineer - which was certainly true, but I'd also done a lot of digital circuit design. I was supervising him at the time, so he might have been being diplomatic, but he been happy enough to improve on my system design where he'd thought (correctly) that it could be improved

That's what made me choose ECL back in the 19880's. ECLinPs didn't get to be available until the 1990's, but it was faster than 100K ECL and available in low inductance surface mount packages.

But with similar side effects. Continuously running oscillators can have much lower jitter. Interpolating between cycles is a pain, but short period monostables can be made pretty good. Tapped delay lines can be much better, but they can't be made continuously variable, except perhaps with lots of varactors.

If you want a fast analog-multiplier based phase detector, building one around the AD834 (500MHz, current output) or the AD835 (250MHz voltage output) will give you all the speed you'd seem to need, but either costs twice as much as the AD9901 - about $35 as opposed to $17 - and would be even more difficult to use.