Phase detector with a MC1496

The kind of mental rigidity that comes from knowing what you are actually doing. A phase locked loop depends on supplying a stable DC voltage to the voltage controlled oscillator to keep the output frequency stable. Non-linearities in the phase detection circuit introduce small DC offsets which get compensated by small frequency offsets. Long term you still get the frequency you need, but those little short term frequency offsets are noise.

Cheap, but not all that great.

Probably one. The question is hilarious. It's certainly a niche part, but it has been around for several decades now. It would be a legacy part, so supply is always going to dubious. There are situations where only a discrete component approach is going to give people the result they need. You don't want to address that kind of market, which is a commercial decision, and possibly a sensible one, but your strategy is to go after niche markets, and that excludes one of them.

We did the master timing system for the highest power laser in the world. We have hundreds of timing modules all over the facility, with a fiberoptic timing distribution network.

For a layman's AI summary, google

nif master timing system larkin

The precision and jitter are a few picoseconds. The timing module PLLs use a d-flop bang-bang phase detector to lock the local VCXOs to the biphase data stream.

A discrete transistor analog multiplier type phase detector would be wrecked by microvolts of temperature-induced offsets. Among other problems, the gain, volts per radian, is just too low.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

If you go the hybrid route there's the BFT977 - siliconsupplies have some nice parts.

Or plenty places will slice and package a wafer.

Thank you.

Conventional pll theory gets a little weird when there is an infinite gain phase detector. Two subtelties are

1. The feedback isn't continuous, it's sampled. So the loop alternates picoseconds or femtoseconds early/late at some suitable duty cycle and
2. There will always be some jitter to make the gain effectively finite.

In my system, I also had two switched loop bandwidths, seek and lock. A very narrowband PLL can get lost if it's very far off lock, and never creep in the right direction toward lock. There's some really tricky math there too. And a tiny DC offset in the phase detector can make things worse.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

There are better master oscillators around. A whisper-gallery mode around a a chunk of sapphire in liquid helium offers rather less jitter, and it is used in Australia's over the horizon radar system, if IEEE Spectrum is to be believed.

It may have been good enough for that job, but you probably should have done better.

If you had used monolithic duals for the crucial transistor pairs their offsets wouldn't have wrecked anything.

My original suggestion was the Analog Devices AD9901, which is an integrated circuit

"

"

That's what op amps exist to correct. The phase output that you are interested in is a relatively low frequency signal, which you could amplify and integrate, if you knew what you were doing.

Floyd M. Gardner's "Phase Lock Techniques" ISBM 0-471-04294-3 does go into this, but doesn't mention the obvious answer, which is two phase detectors - one a reliable digital phase detector which you use when the loop is out of lock, and a second analog phase detector which takes over when the loop is close to lock. Gardener's book was written in 1967, back when computers used magnetic store memory. Having a small microprocessor in the circuit to switch from one phase detector to the other wouldn't have been practical back then.

None of his later editions mention the 4046 which included three phase detectors, not that they were designed to be used that way, and would have a taken a little ingenuity to adapt to that mode - I did work out a way at one point, but never reduced it to practice.

There's always going to be a tiny DC offset in the phase detector. You do have to design around it. One option is to swap phases regularly - as you can in an AC system - and let it average to zero.

Am 19.10.25 um 10:39 schrieb Jan Panteltje:

Yes, like Walter Bruch's PAL system (Phase Alternation by Line) which was a huge improvement over Never Twice Same Color.

That converted hue errors to brightness errors that were not so visible by far.

Gerhard

But that was a much older scheme.

And sometimes it went wrong. For a couple of years one of Cambridge Instruments electron microscopes generated 623 line TV, which recorded fine on regular tape recorders but messed more precise machines.

One of my colleagues set up a bunch of counters that let him show that it was generating a 623 line frame, and I dug into the timing PROM responsible and found the handful bits that had been mis-programmed at some stage, and was able to correct them. It was all slightly comic, but should never have happened.

Good to know that they exist, thanks.

A bit of an uphill sell for customers, I expect. :(

Cheers

Phil Hobbs

For everyday clock locking, we do that in an FPGA where we have unlimited resources. My guys have some scheme where far-out is detected and always walks toward lock, and switches to xor in lock.

They tried the 4096 style charge pump but that didn't work well in an FPGA. It doesn't work well in the 4096 either.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

We got an award. And some VIP tours. And some checks.

Of course they would. A tiny offest rails a PID loop, and a railed loop won't lock.

You'd be amusing if you weren't so nasty and so sad.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

How so? Why would it rail? As far as I can tell, it would merely cause a steady-state phase error, probably a small one. The integrator in the PID can rail, true, but it should recover eventually. You have to use a phase-frequency detector though. A simple EXOR may indeed fail to lock.

Jeroen Belleman

What on earth is the 4096? Did you mean the 9046?

You may have unlimited digital resources in an FPGA, but there are some tricks that FPGA's aren't designed to do.

And an exclusive OR isn't an analog phase detector. Devices like the MC1496 exploit the signal you are locking to over a longer period than just the zero-crossing, and can generate can less phase noise in consequence, if you design the circuit sensibly.

Sensible people keep their suppliers happy.

You idea of what might be "decent" isn't to be relied on. And my designs were mostly commercial in confidence.

The whole point about a PID loop is that it generates feedback. The analog versions are all built with op amps that do have offsets, and the feedback makes sure that they don't drift off into the rails.

Depriving you of the flattery that you crave might be seen as nasty. But indulging your pretensions would only encourage you to post even more fatuous nonsense.

An MC1496, or an equivalent made from a transistor array, is not a phase-frequency detector.

Frequency already integrates into phase. Add a PID and the loop has two integrators. Tiny phase detector offsets will rail such a loop. If it's very far from lock, it won't ever lock.

An xor is mathematically similar to a 1496, basically a multiplier, just cheaper and more linear.

Out-of-lock is a very different situation than in-lock.

There is a simple logic circuit that we use in FPGAs that can tell whether a VCO is above or below a reference frequency. That can be used to slew the VCO in the right direction so that an XOR or bang-bang flop can take over close the loop. I proposed doing it with counters but my guys found something simpler.

A simple mutiplier like the 1496 is fine if the loop bandwidth and the pull range and the maximum possible frequency error are all controlled. But a temperature change or some ageing may break it.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

I didn't really think you had a PLL circuit to share.

That's a standard dodge, claiming that some nda or something prevents people from posting circuits.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

I meant the CD4046. I haven't used one in at least 30 years.

The first page of that data sheet says "charge pump"

and it doesn't seem to me to be the sort of

Google AI thinks that pd2 is a charge pump too. It's pretty bad.

We tried the pd2 logic in an FPGA; just pull up or pull down open-drain to charge pump. But the jitter performance was bad.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Depends on the loop filter and the tuning range of the VCO.

If the beat note is too far down the rolloff, offsets can make it rail, and if the second pole is too close-in, the phase shift can make the pull-in voltage have the wrong sign, causing false lock.

But a couple of millivolts of output offset from the phase detector aren’t usually a big problem, and anyway, an acquisition aid takes one SC70 op amp and two resistors.

I agree with you that the knife-edge PD response of the PECL dflop is a huge win for that job.

Cheers

Phil Hobbs