OT: Silicon oxide as a switch

Ovonics?

On a sunny day (Fri, 03 Sep 2010 01:07:04 -0700) it happened Robert Baer wrote in :

I looked up that word,

seems to apply :-) Still, if this thing goes into mass production, maybe say goodbye to Blu_Ray and other mechanical [RW} media.

10000 x rewritable is not bad at all.

Latest graphene transistor clocks in at 300GHz and is good down to nm scale. HP commercializing memristors, good down to at least 4nm. Moore's Law continues for at least another 30 years it seems.

--
Dirk

http://www.transcendence.me.uk/ - Transcendence UK
http://www.blogtalkradio.com/onetribe - Occult Talk Show

Ovonics has been the memory technology of the future for decades now.

Yikes!

John

On a sunny day (Fri, 03 Sep 2010 16:41:26 -0700) it happened John Larkin wrote in :

You are just a troll. plonk

Nope. The wires have been slower than the transistors for awhile now, even on-chip, and the power consumption is still a big big problem.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
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hobbs at electrooptical dot net
http://electrooptical.net

So turn the whole damn thing into transistors. Make it, like, a very long (wide) SCR, so the signal zips along. No regeneration needed, no RC delay, it's an active transmission line!

Maybe there's a way to trap a transmission line between biased junctions so it gets active charge injection with a negative resistance characteristic. Or bring back degenerate doping so it's a tunnel diode.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

On a sunny day (Sun, 5 Sep 2010 09:02:59 -0500) it happened "Tim Williams" wrote in :

IIRC much of the power consumption comes from those transistors not being 100% 'off'. Is there not some thing like: want to move less charge -> need lower voltage -> less gate drive -> more on? Shoot through? Or something like that :-)

The "100% off"-ness arises from the insulators and junctions being so damned thin that current tunnels through. A very thin insulator doesn't insulate very well. So it's leakage across parasitic PN junctions, across gates, across not-quite-off channels, etc.

Come to think of it, I seem to recall reading that junctions *are* doped to degenerate, or nearly degenerate, levels, a necessity because there might otherwise be only a few atoms of dopant in the ~45nm square junction. Maybe my point about tunnel junctions isn't far from the mark after all?

I don't know what threshold voltages are like these days. Obviously, they're in the 0.5-1V region, but I don't know how much overlap there is for typical 1.2-1.8V silicon. It probably doesn't matter, internal switching speed must be in the ps range, so shoot through is relatively negligible.

I also don't know where it zeners; I'm willing to bet they self-destruct past 3V or so.

The nice thing about tunneling, at least, seems to be that it doesn't scale at the same rate as processing power or speed. Hence, very fine pitch cores like the Atom take even less power, and run faster, than the previous scale models.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

On a sunny day (Sun, 5 Sep 2010 10:44:10 -0500) it happened "Tim Williams" wrote in :

OK, I stand corrected. Maybe the tracks in the chip can be configured as transmission lines ? ;-)

Trouble with that is, silicon is lossy and capacitey stuff, and the traces are thin, so it's more of an overdamped (RC) transmission line, not a proper LC. This makes really awful signals when it has to go all the way around the chip or something. Sometimes, they'll add a regenerator (which could be a buffer or chain of inverters, or a weak buffer tied to itself for bidirectional lines), which I suppose consumes more power and adds more delay. Hard to guess if it's more delay than the RC line itself has. I can imagine all those RC delays, combined with unknown threshold voltages (like 1/3-2/3 supply), makes for a wide range in propagation delay skew.

Bad inductors can be made, for instance by shielding the silicon with a metal plane in the first layer, then skipping about 6 layers (out of maybe

8 layers of aluminum and SiO2, so the interconnections are stacked high), so there's some high Q air gap, then putting the transmission line or coil or whatever over the top of that. There's only a few hundred nm of airgap, so the available volume is extremely small and only useful at extremely high frequencies in the GHz, where you have little choice but to fabricate things monolithically anyway. Seems like something handy for InP monolithics (which are used for 100GHz+).

For transmission lines, you make a sort of trench, with vias and traces going up through all layers on the sides. Just like doing microstrip on a PCB, you run ground traces alongside the signal trace, with vias joining the grounds along the way.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

One thing people are investigating as a way to get around the problems with metal traces as linewidths and film thicknesses continue to shrink is moving to optical interconnect systems. Think a nanoscale fiber optic network dropped on to an IC.

In addition to the obvious integration issues (What do you use for an optical source? How do you make your optical waveguides withstand subsequent processing? What do you use for photodetectors?) there are less obvious problems such as "How tightly can you bend the waveguides?" (In tight bends, the light tends to escape.) and "How do you minimize loss at splits?"

Upsides are: "Who cares about RC delays?", no problem with EMI or other electrical interference and (hopefully, at least) less power consumption.

Bob Pownall

And as I recall, Phil was playing with that. Not-quite-near IR goes through silicon nicely, so waveguides are a piece of cake. Detectors can maybe be made with germanium or what compatible compounds there are, or nanocomposites, etc. LEDs can be made with compounds or nanocomposites.

Isn't there a wave propagation mode where you bevel the corner and it basically reflects off it, line of sight? Of course, you can't have anything immediately adjecent to that corner (photon tunneling), so it needs to be well shielded (possible waste of aluminum), or well etched (for total internal reflection mode). On the plus side, you can take advantage of the wave nature by using half wave spacings to make "supermirrors". Using a null spacing has less coupling than absolute distance would otherwise suggest.

Tim

-- Deep Friar: a very philos> problems.>

I'd really like to see a 20nm wide waveguide for radiation that is some

40 times larger in wavelength

--
Dirk

http://www.transcendence.me.uk/ - Transcendence UK
http://www.blogtalkradio.com/onetribe - Occult Talk Show

'off'.

A current coworker (used to work for intel) say that leakage power exceeds switching power since the early pentiums.

In part, that is a false analogy. AFAIK, no one is even *TALKING* about

20nm wide metal lines. Any references you might see to "20nm technology" refer to minimum feature size - gate widths and contact sizes. Intel's published specs for its 32nm process quote a 112.5nm pitch (line+space) for metal-1 and a 566.5nm pitch for metal-8, which is where clock and related signals would probably be routed. (Metal-9, which is the top metal layer, is quoted as a 19.4um pitch, and would probably be used for power and ground. Note: That's microns, not nanometers.)

So, with a 566.5nm pitch, we're probably talking lines ~280nm, so we're within a factor of around 2.3 (for red) to 4 (for IR) of the radiation wavelength. In fact, you don't WANT optical waveguides that are much wider than the wavelength of the radiation, because then you can get multiple propagation modes down the waveguide, which leads to signal "smear".

In addition, it's possible to improve the waveguide confinement of an optical waveguide by increasing the index contrast between the cladding and the core. i.e. Going to a higher index core, a lower index cladding, or both. This fits well into the existing trend towards low-k backend dielectric films.

Bob Pownall

[snip]

My experience with 45nm FPGAs has been that leakage current will account for about 1/3 of my power budget in the part. This will get worse as they shrink, only partly ameliorated by the use of hi-K dielectrics.

Regards, Allan

I'm not buying that statement. That would mean the best a low-power mode, without switching power to the logic, can do is 50%. That's clearly not the case.

FPGAs aren't a good example; too much ancillary stuff that's not clocked with the system clock but will still leak and too much stuff that has different geometries (for this reason). Of course, all of this depends on the particular circuit. Processors are array rich (as are FPGA, on second thought), which is different than pure logic.

Your point on finest features is reasonably well made. The optical emitters and detectors will be on the silicon surface instead of the high metal layers, nor will the geometries be in the vicinity of minimum feature size.

Please do a comparison with standard 9 micron singlemode fiber optic and standard 1310 nm and 1550 nm to the proposed silicon surface emitters and detectors required for on chip internal optical connects.