Silicon Design

how about this?

martin

Ah, a start!

Tim

-- "Librarians are hiding something." - Steven Colbert Website @

just

Yup. You get crappy, damaged silicon.

LCDs and such grow silicon on glass, poly or amorphous, and it makes slow, leaky transistors, just good enough to drive pixels. Ditto the low-efficiency solar cells used in calculators.

John

3D silicon is an active development area. Stacked memory has been available for ages, but afaik it has always done by wire bonding, so it isn't really 3D. The silicon through-via technology has been developed independently in several places--earliest at IBM, I think. It's useful because you can run interconnects through stacked chips like elevator shafts in a tall building. The problem has been not so much in drilling the holes, as in filling them with a reliable metallization at a very dense wiring pitch.

We (IBM) have a silicon-carrier technology that allows the use of IC-type wiring densities in first level packaging. At one point we were considering splitting large ASICs up into tiles, and putting them on silicon carriers. That's expensive in processing, but you more than make it up in yield, due to the smaller area of the individual tiles. I don't know if that ever made it into a product offering.

It's possible to do epitaxy over top of fabricated devices, but I don't think that's what will show up in the first real 3D devices, anyway. The main problem is yield again--instead of, say, 600 process steps, you'll have 1000 process steps, and keeping the yield up through that is really, really hard. Wafer bonding improves yields, because you only bond good wafers to good wafers.

Chip-level optical interconnect is intimately involved with 3D issues, because the transistor folks won't let us play on their real estate--we have to live on a separate silicon level.

Cheers,

Phil Hobbs

Thanks for that, I just this

Fun times ahead

martin