In this circuit, it looks like current passes through the load in both the ON and OFF positions. Assuming an N-channel enhancement mode FET:
When switch is closed with application of Vg > Von to gate, FET does not have opportunity to conduct do to exponential characteristic of diode limiting drop to ground to approximately 0.7v, so current through load is [12-Vdiode)]/Rload.
When switch is open with application of Vg < Von to gate, FET is off, and current through load is [12-Vdiode]/Rload.
Assuming NPN BJT insted of NFET, you would also have to limit current through the base-emiitter diode.
Depending on your load, which probably has relatively high resistance, I don't see what a FET with a low Rds(On) wouldn't work.
I thought the same thing until I noticed that the OP has a GND separating the 5-volt branch from the rest of the circuit, which if meant to be present, would make that part of circuit irrelevant, hence chance for misinterpretation.
I guess it would help to know whether the GND was meant to be there or not.