Hello,
I would like to build the switch in the following circuit using small signal transistors:
5V +-------+ +---- GND | | | | | | o /o / / o | | .-. | | | | LOAD '-' | | | 12V ---------+Any tips on how to go about this with a few discretes would be most appreciated.
Thanks,
Jon
It's easier to visualize stuff like this if it's drawn with the current flowing down, namely with the +12 at the top.
John
signal
Sorry 'bout that. Thanks for the help; that is a very nice and simple solution.
Thanks,
Jon
In this circuit, it looks like current passes through the load in both the ON and OFF positions. Assuming an N-channel enhancement mode FET:
When switch is closed with application of Vg > Von to gate, FET does not have opportunity to conduct do to exponential characteristic of diode limiting drop to ground to approximately 0.7v, so current through load is [12-Vdiode)]/Rload.
When switch is open with application of Vg < Von to gate, FET is off, and current through load is [12-Vdiode]/Rload.
Assuming NPN BJT insted of NFET, you would also have to limit current through the base-emiitter diode.
Depending on your load, which probably has relatively high resistance, I don't see what a FET with a low Rds(On) wouldn't work.
-Le Chaud Lapin-
Just pretend you're a Physicist ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
When the fet is on, the diode is back-biased and out of the circuit. The fet saturates as well as it can, so current is (12-Vsat)/Rload or maybe 12/(Rload+Rdson).
No, the current is (7-Vdiode) / Rload
The 5 volt supply does need to be able to sink Iload.
John
I thought the same thing until I noticed that the OP has a GND separating the 5-volt branch from the rest of the circuit, which if meant to be present, would make that part of circuit irrelevant, hence chance for misinterpretation.
I guess it would help to know whether the GND was meant to be there or not.
-Le Chaud Lapin-
Or an arabic engineer, with signals flowing from right to left!
I like to draw with positive supplies high on the page, and current flowing down. That places PNP emitters up and NPN emitters down. Signals flow to the right, feedback to the left.
John
I think it's a font problem. I think he meant...
5V +-------+ +---- GND | | | | | | o /o / / o | | .-. | | | | LOAD '-' | | | 12V ---------+John
Yes, that is what I had meant to paste in originally, thanks.
Jon
[snip]
Same here, actually. I was just yanking your chain ;-)
I'm really picky about schematic format... I like to draw so that it's quite obvious how signals flow and how circuits work.
So I spend quite a lot of time cleaning up drawings to avoid clutter and confusion.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
An n-channel enhancement-mode FET pesents a conducting path when a positive voltage is applied to its base and presents an open circuit when the applied voltage is zero.
A p-channel depletion-mode FET presents an open circuit when a positive volage is applied to its base and presents a conducting path when the applied voltage is zero.
Take these two devices, tie their drains and together and attach the drains to the oad. Tie their bases together to receive control signal. Tie one source to 5V, the other to GND.
-Le Chaud Lapin-
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