Noise of a comparator?

Jun 26, 2009 4 Replies

In the datasheets, they rarely provide any specs regarding the noise performance of the comparators.



Would it be reasonable to assume that the noise of the fast comparator is similar to the general purpose bipolar input stage? Can we speculate about the noise based on the bias current?



More intricative question: what is the efficient noise bandwidth of a comparator? Would it be valid to assume that the noise bandwidth is at the order of 1/(2*Pi*propagation delay) ?



Practical observation: the noise of a CMOS logic gate used as a comparator is about 6dB higher compared to the typical high speed comparator IC.


Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Seems reasonable to me.

IIRR it's the emitter current in the input transistors that sets the noise level, rather than the base current, and the bias current isn't always just the basecurrent.

Probably not. The orignal Am685 had a propagation delay of 6.5nsec - through three stages of gain - which translates into a bandwidth of

24.5MHz, while its gain started rolling off rapidl at about 100MHz (as shown on the data sheet) with all three stages of gain rolling off at the same sort of frequency.

CMOS transistors tended to be noisier than their bipolar equivalents - IIRR it had to do with contaminants in the insulator between gate and channel. I do believe that manufacturers can make quiet CMOS transistors, but they are unlikely to go to the troulbe when building CMOS logic gates.

-- Bill Sloman, Nijmegen

It is reasonable to assume that it is effectively worse than an op-amp input with the same current, but that it is better and worse from comparator to comparator for the same reasons.

I think that the LT1016 datasheet or ap-notes tells you the number for it. The delay from input to the output is more than a single pole so I'd expect the bandwidth to be a few times the number 1/ (2*pi*something) will give you. It may be even more if the part contains any positive feedbacks.

For what it's worth, a good 1 ns ECL comparator can be hung on a linear ramp (cc source charging a capacitor) in the ballpark of 3 volts swing, and used to generate programmable time delays, with RMS jitter in the ballpark of 20 PPM of the ramp time... 2 ps RMS jitter for a 100 ns range. That's something like 60 uV RMS equivalent noise, maybe 2 nv per root Hz, if I did all that right.

John

Other than operational amplifiers, comparators are expected to tolerate larger differential input voltages so I suppose that at least some of them have current limiting resistors in the input leads.

OpAmps like ad797 have limiting diodes across the inputs, but the resistors are omitted because they would spoil the noise specs.

regards, Gerhard

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