Hysteresis Comparator Methods

This appnote is seriously bogus, in that it totally ignores the time-domain aspect of the positive feedback. Figure 7 is especially pernicious. Unless very carefully thought out, including consideration of the slew rate and noise characteristics of the input signal, the conventional hysteresis circuit can propagate glitches contrary to its claimed bahavior.

This appnote is a great example of simplistic, intuitive analysis that's just wrong.

This can be a lot better, because there's no delay coming back around into a positive-feedback node, and because the comparator prop delays are effectively pipelined... everything flows left-to-right. The comparators still have to be well behaved and well characterized, specifically to have fairly symmetric rising and falling edge prop delays. But this configuration has fewer screwup modes.

The other nice thing here is that the two comparator references can be programmed with DACs, allowing thresholds and hysteresis to be under software control. I use this configuration in my tachometer conditioning modules, and it's very flexible.

John

Then there's the optimum method I devised in my MC1650/51 design in the mid '60's ;-)

...Jim Thompson

Hysteresis internal to ICs can be a lot better, because you can localize the positive feedback into a very tight, single-pole loop. The HC14 type schmitts are apparently immune from teasing, too.

Opamps often make better comparators than comparators, because they have one dominant pole and don't store as much information as the usual fast-multistage comparator topology.

It's funny that the common comparator-plus-hysteresis circuit is almost universally taught as being a clever thing, taught by people who don't understand it.

John

One thing I don't understand is why you Old Blokes bolloxed on about comparators with hysteresis and then gave us comparators with hysterectomies...... and we still have to deal with them.

DNA

The MC1650/51 has BALLS ;-)

...Jim Thompson

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

from BC)

the

especially

consideration

signal, the

contrary to its

analysis

are

stable

latch

app

back around

prop delays

The

characterized,

prop

references can be

be under

design in

can

loop.

too.

they

the

is

people

One thing I don't understand is why you Old Blokes bolloxed on about comparators with hysteresis and then gave us comparators with hysterectomies...... and we still have to deal with them.

DNA

------------------- Great! Looks like this cct. is a "sports car" of hysteretic compartors.

I'm now more suspicious of app notes. Trust nothing. :)

Got curious and looked up the MC1650.. Dual A/D converter??.. Huhhh...Still have alot to learn.. :) Internally it's in the design "ball park" of interest.

Op amps make better comparators!! Looks like I picked up a myth..In my internet travels, I recall reading that comparators are best in comparator applications.. I haven't yet compared op-amp/comp internals and specs. Just blindly running on rumour.. It's a good thing I don't design life support systems :)

My next move is to take a look at the various IC's containing a combo of op amps (or comparators) and a D latch to make a hysteretic comparator. CMOS would be nice..

Thanks for the verification.. D

------

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Oh Great

What's the point of having balls if you haven't got the c*ck to deliver it? I will not mention the sexual aspect of this stuff........ Mr pico second.

Us thickos want a comparator where we can set the up and down stuff about the somewhere else without using our branes.

DNA

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

wrote in

(D from BC)

as:

the

especially

consideration

signal, the

contrary to its

analysis

are

stable

latch

in app

back around

prop delays

right. The

characterized,

edge prop

references can be

be under

design in

can

pole loop.

too.

because they

as the

circuit is

people

about

Oh Great

What's the point of having balls if you haven't got the c*ck to deliver it? I will not mention the sexual aspect of this stuff........ Mr pico second.

Us thickos want a comparator where we can set the up and down stuff about the somewhere else without using our branes.

DNA .

------------ Talking about picoseconds... I recently came across this speedy op amp with a hysteresis control pin.

I didn't name it. Back in those days Motorola had a department that did data sheets. I think the name derived from the 64-wide version I made for WPAFB for a flash converter.

Yep. My 1965 speed numbers compare favorably with today's designs.

I think it's a myth too.

I've done several comparator plus D-latch (or even S-R) versions in CMOS.

But they're custom ASIC's.

...Jim Thompson

There's always the 555 :)

Thomas

I'm not sure how well the circuit with the mosfet steering will work. At some point, both fets will be on.

I'd like the longer description.

In regards to using the 555 as a hysteresis comparator....

The 555 is a great suggestion. I'm somewhat stuck using those internal resistors. But that might turn out ok...Will be checking specs. Nationals LinMos sounds like an improvement to the 555. It's one of the few IC's I know of with comparators and a latch. D

As requested, longer description for 2 comparator & latch cct to make a hysteresis comparator.

Kinda like the 555. D

Which comparator is peak and valley. [Non-inverting and inverting?] Do I need to know what is dominant (set versus reset, etc.).

I really don't like a comparator driving the CLK unless the rise/fall times are known to be fast enough not to cause problems.

The other thing to consider is many circuits these days run synchronous, so the comparator can just be sampled with a DFF based on the master clock. I'm not sure if I'm explaining this well.

As requested.. Updated description for the 2 comparator&D type latch hystersis comparator cct.

A signal is applied to + input of a comparator. This is the "peak" comparator. It's output connects to Clk and Set of the latch. The - input gets a ref voltage.

Same signal is applied to the - of another comparator. This is the "valley" comparator and its output connects to D and reset of the latch. The + input gets a ref voltage.

For conserns of comparators driving latches: There's comparators with 1.2nS rise and fall times.. Hopefully good enough...

In my original post, I mentioned that I'm not familiar with this means of creating a hysteretic comparator.. I haven't thought about the timing to the latch yet. I'll be examining this circuit further once I've eliminated other competing methods.

About the sampled comparator& mater clock... Sorry, too foggy for me..dunno.. I seen comparators with build in hold functions..

You can do the same thing with a simple SR latch (cross-coupled NAND gates) if you get the comparator polarities right.

If upper comparator says sig>hilim, set the latch.

If lower comparator says sig

A variety of noise-blanking circuits using S-R Flops or the 555 equivalent are shown in an old posting at....

I used a device equivalent of the last circuit to "shield" automotive ignition pickups from spark noise in 1968.

...Jim Thompson

Conserning use of comparators and SR latchs to make a hysteresis comparator..

I'm keeping an eye on that SR latch idea.. The SR latch has that illegal input state (race condition). My spec is 100mV of hysteresis and this circuit is part of a smps controller.. Could be like finding a quiet spot in a noisey dance club :)

I suspect as hysteresis approachs 0 there's more probability that the SR latch gets simultaneous S and R signals due to noise presented to the comparators. Just getting scared by this quirk, but I won't rule it out yet..

I had to review my latch operation and found:

For choice of latch in the circuit... Perhaps SR is good for wide hystersis and clean signals and D latch for small hysteresis and dirty signals??

Conserning

Cooooll...to see the good ol'555 not used as an oscillator..

Thanks D