Hi,
Taking for example a microcontroller reading a RAM device - the datasheet for both the microcontroller and memory show 'best and worst' case timings for the bus signals. For example the RD~ line will go active between 2ns and 6ns after the clock edge.
When will this variation occur?
Is it ...
Always the same for every identical device in that for one device the RD~ line will always go active 4ns after the clock edge on *every* bus access while another device (same part number) it might *always* be 6ns for every clock cycle. In this case the timing for each device are different, but the timing within the same device is always the same.
or ...
Will this variation be seen on a single device - in that taking a single device the RD~ may go active 3ns after the clock edge for one cycle, and then 4ns after the clock edge on the next. In this case there is variation even in one particular part.
Whichever is the case for microcontrollers, is the same true of FPGA's.
Thanks for any comments!