Negative Capacitance

Odds are about 10000:1 against.

Why? I don't know enough about the physics so I am legitimately curious as to what the problems will be.

It would be nice if it worked out. Chips will need to move to using 3d transistor below the ~5 nm feature level because of source drain tunneling, but they have higher intrinsic gate capacitances than the planar geometry. Use negative capacitance to reduce it.

Basically the device that generates the negative capacitance has to be much faster than the one you're trying to compensate, or else you get a lot of negative conductance...i.e. the whole thing oscillates. So if you have something that fast, use it instead.

Been there, done that, got the T-shirt.

Cheers

Phil Hobbs

That's roughly the ratio of silly press releases to actual things that are worthwhile. There's an entire industry cranking out announcements of scientific breakthroughs.

e-changer?

Nature publishes peer-reviewed scientific articles, not silly press release s. They show up in the Murdoch press, aimed at the unsophisticated audience of which you are painfully representative. You don't know enough to apprec iate the distinction, but many of our posters are aware of the difference.

As bitrex says, it may strike somebody as the solution to their particular problem, though - as Phil Hobbs says - it may have practical limitations wh ich make it useless.