Why do JFET/FET amps experience the miller effect? There isn't any feedback

There is a capacitance between the FET drain and gate. This arises due to the fact that the gate and channel are separated by only a PN junction. That capacitance acts as a feedback element. So your premise, "don't have feedback", does not apply. (Your conclusions would be sensible, otherwise.)

It also arises from the capacitance of the silly plastic breadboard thingie.

John

good point! Thanks to all.

I read in sci.electronics.design that Stephen wrote (in ) about 'Why do JFET/FET amps experience the miller effect? There isn't any feedback', on Tue, 12 Apr 2005:

There IS feedback, via the drain-gate capacitance. This is analogous to the very original Miller effect, due to the anode/plate-control grid capacitance in triode valves/tubes.

Note and admire the bilingual exegesis. (;-)

If the gate voltage goes down by a small amount, the drain voltage goes up by that amount multiplied by the stage gain. So the capacitor demands charge as if it had a capacitance larger by a factor equal to the stage gain.

What? ?8-\