Could someone explain why a self biasing JFET amp (for example:
of a impedance across a negative gain device."
In Erno Boberly's great article "JFETS: The New Frontier Part I"
Thanks Stephen
Could someone explain why a self biasing JFET amp (for example:
of a impedance across a negative gain device."
In Erno Boberly's great article "JFETS: The New Frontier Part I"
Thanks Stephen
There is a capacitance between the FET drain and gate. This arises due to the fact that the gate and channel are separated by only a PN junction. That capacitance acts as a feedback element. So your premise, "don't have feedback", does not apply. (Your conclusions would be sensible, otherwise.)
-- --Larry Brasfield email: donotspam_larry_brasfield@hotmail.com Above views may belong only to me.
It also arises from the capacitance of the silly plastic breadboard thingie.
John
good point! Thanks to all.
I read in sci.electronics.design that Stephen wrote (in ) about 'Why do JFET/FET amps experience the miller effect? There isn't any feedback', on Tue, 12 Apr 2005:
There IS feedback, via the drain-gate capacitance. This is analogous to the very original Miller effect, due to the anode/plate-control grid capacitance in triode valves/tubes.
Note and admire the bilingual exegesis. (;-)
If the gate voltage goes down by a small amount, the drain voltage goes up by that amount multiplied by the stage gain. So the capacitor demands charge as if it had a capacitance larger by a factor equal to the stage gain.
-- Regards, John Woodgate, OOO - Own Opinions Only. There are two sides to every question, except \'What is a Moebius strip?\' http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
What? ?8-\
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