Vgs nmos turn on voltage

From Figure 1, VGS > ~5.5V has very little improvement in Rds_on

How serious are your needs for low Rds_on? ...Jim Thompson

=A0 =A0 ...Jim Thompson

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=A0 | =A0 =A0 et =A0 =A0 =A0|

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=A0 =A0 =A0 |

not very serious more just trying to understand does it matter how high I go with my Vgs? 12V better than 9V ? that kinda thing

Depends on your definition of "better" ;-)

Minimal improvement in Rds_on. More gate swing, if done at a high rate equals more drive power consumed. ...Jim Thompson

Those are the range of what to expect from lot to lot and condition of operations. If you're using this as a switch, I'd be well above the MAX Vgs(Thr) voltage to turn it on. Also, gate charge and your driving device has a lot to do with it so to not hover to long over the threshold point, otherwise, this can cause heating of the FET due to it being in the linear region for too long.

That part there is best used in a 5v or more logic switch signal, I don't think it would be a good idea to use that in a 3.3V logic level system, unless of course, you plan on using a gate driver with a charge pump in it.

Jamie

--- From the data sheet's "On Characteristics", Vgs(th) - the gate threshold voltage - is defined as that voltage which, when applied across the drain and source, with the gate and drain tied together, will cause 250 microamperes of current to flow through the MOSFET.

That voltage is specified as being anywhere between 2 and 4 volts, and is the voltage required to get the MOSFET to just start to turn on with 2-4 volts across it and the gate and drain shorted.

More meaningful with respect to your drive voltage question is the Rds(on) spec, which states that with 10 volts between the gate and the source and 3.9 amperes of drain current, the drain-to-source resistance will be a maximum 0f 360 milliohms ohms.

That's just a single point, of course, but it serves to state that with 10 volts between the gate and the source, the resistance between the drain and the source will be at its minimum.

Study figures 1,2, and 3 on the data sheet in order to get a better feel for what happens with other gate voltages and drain currents.

Just as an aside, the active silicon area between the drain and the source is called the "channel", and when a small increase in gate voltage no longer elicits a correspondingly small decrease in the channel resistance, it's said to be "fully enhanced".

For most MOSFETS, the channel will be fully enhanced at somewhat less than 10V, but for "logic-level" devices that voltage will be somewhat less than 5V.

-- JF