more AD7793 fun.

I ranted previously about the buggy SPI interface of the Analog Devices AD7793 delta-sigma ADC part. We wound up kluging a cap to ground on the SPI clock line, which seemed to fix the SPI hangups. We also reset the chip (by sending 32 1's) every measurement, to un-hang it if it does hang up.

Now we're seeing huge zero offsets. On the gain16 range, we're seeing hundreds of microvolts of offset, and the magnitude and even sign can change depending on what signals we mux into the differential input. Common-mode rejection is terrible too.

After a week of experimenting, we found that hacking a 33 nF cap directly across the diff input pins fixes the offset. There must be some weird charge injection thing going on.

We understand neither fix.

The part is terrible and the data sheet is terrible. ADI should fix both, but they probably won't.

In general, cmos chopper/zero-drift architectures seem inclined to charge injection errors that data sheets are careful to not mention.

--
John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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John Larkin
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Or RF noise getting in?

If there is any diode path such as back-to-back protection diodes you could also see RF rectification effects. Sutro Tower comes to mind. But in that case the offset should change when holding metal over the unit. Unless it's a big AM station getting in.

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

I bet the eval board for this part works ok. Have you considered that you may have noise problems on your board? All the bandaid caps sure make it seem like that.

--

Rick
Reply to
rickman

We think not. We've tried adding antennas here and there, and pawing everything, and playing with the box cover, and the offset doesn't change. Oscilloscopes show about the normal level of fuzz.

We suspected that a lot of RF could bang ESD diodes inside the chip, but our common-mode voltage is 2.5, with a 5 volt supply, which means we'd need a huge amount of RF, which we don't see.

I don't want to invest more engineering to understand the problem; it's fixed for now. We will kluge and ship, and eventually spin the board and use a TI part.

--
John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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Reply to
John Larkin

RF rectification can oocur at any junction, not just the ESD diodes.

Mark

Reply to
makolber

The classic scenarios are BE junctions at the first pair. Could be CMOS here though which avoid that problem. The other scnarios is rectification and protection diodes between amplifier inputs which are really never reverse-biased. But it's unlikely here and since John did the "hand-waving" and saw no effect it's even less likely. So maybe an internal bug.

formatting link

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

"cap to ground on the SPI clock line"

How does this not sound like a noise problem on the board or other signal integrity issue? What else could it be?

--

Rick
Reply to
rickman

It's a CMOS part, so presumably doesn't have bipolar transistor junctions. There are burnout-current and common-mode-voltage supplies, which might involve some junctions somehow. But experiments that should have modulated ambient RF levels had no effect, which is why I suspect CMOS charge injection issues.

Anyway, I wanted to warn the world. Google may index this.

We need a web site that collects and posts IC bugs. Anybody interested?

--
John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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Reply to
John Larkin

It is not the first time. I've had chips before where the required SPI timing was, ahem, politely said, not quite what the datasheet says it was. So we also had to scoot one of the lines versus the other. After a layout is done a cap might be your only quick-and-dirty option.

That is the "else" in what it could be.

No idea if the case here but in general I've seen such effects inrease over the last 15 years and often with chips designed in Outsourcia.

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

"Scoot"?

--

Rick
Reply to
rickman

Western US speak for move :-)

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

I understand the meaning of the word. *Why* would you need to scoot a trace? Too much capacitance, too little? Adding length to as a delay?

--

Rick
Reply to
rickman

Not the trace, the signal. I don't remember whether it was the clock or the MOSI line but on one of them we had to delay the transitions to make it all work. Only for the AD chip because it did not like the standard timing. All others worked fine either way.

--
Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

ip,

s.

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an

AD7792_7793.pdf

I
a

yeh, having to add delay suggest a screw up by using the wrong clock edge

but adding a cap could also help slow things down to avoid reflections and double clocking

-Lasse

Reply to
Lasse Langwadt Christensen

So here's one:

1) Desolder all the AD7793. 2) Replace the AD7793 with a part that works. 3) Properly dispose of all the AD7793.

Life's too short...

FWIW, last A/D thing I worked on required using two (T.I.) A/D* channels and taking the difference en soft'ware rather than using it in differential mode.

*which had no impact on the hardware.... differential mode used both anyway or something something.

Because offsets.

They wouldn't let me throw the [expletive deleted] things away.

--
Les Cargill
Reply to
Les Cargill

Yes, most devices allow you to specify the clock phase and polarity via some register. So there's a chance it's wrong at the start. You get extra bonus problems if you try to cascade some 74/4K series shift register because none of them is an exact fit. those discrete shift regs tend to shift-in and shift-out on the same clock edge, so a clock race is more likely with those(but not all of them).

Reply to
Johann Klammer

ge

ome register.

er

hift-in and shift-out

all of them).

afaict most of them have substantially longer Tpd than Th so it should be safe unless you have very long wires

defensive approach is to route the clock in the opposite direction of the d ata

-Lasse

Reply to
Lasse Langwadt Christensen

I can't help you at all, but it sounds like this IC is ready for the "float test". (from a navy tech I knew in grad school.)

Throw it in the lake/ocean* Huh, doesn't float, we can't use it then.

George H.

*if needed, you can tie a stone to whatever you are "testing".
Reply to
George Herold

It doesn't, but it does raise the threshold voltage, With bipolar junctions you need about 50mV of high-frequency signal to push the pair into non-linearity, while pairs of field-effect transistors need something closer to a volt.

--
Bill Sloman, Sydney
Reply to
bill.sloman

That would be hard to imagine with logic on the same board. The logic output will have a delay of some nanoseconds so would hardly be race condition unless you also buffered the clock. Easy to use the method used on chips to prevent the clock/data race, run the data in the forward direction and run the clock trace in the opposite direction.

--

Rick
Reply to
rickman

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