power supply oops

Yeah, lots of linears won't start up if you pull their outputs through ground. A BAT54S cures a lot of dual-supply ills. ;)

I'm finishing up a fancy diode laser controller for an outfit in Finland that would probably have a lot of those sorts of issues if it weren't for strategically sprinkled Schottkies.

That diode is potentially pretty useful, I agree. A good thing to have in the kit, for sure.

Cheers

Phil Hobbs

Huh, nice. I stuck a Schottky (1N5817) on the gate of 'my' thermal FET so that it wouldn't go too negative. It reduced the 'leakage' current some.. (3 mA to 0.3mA) but still not enough.

George H.

Did everyone forget the first thing about electronic design ? God damn I thought I was in the company of qualified folks. Jeez, I know better.

You are the engineer, the designer of the circuit. You are responsible for the power up and power down cycle of this device.

You just forget that when convenient ?

Everything you design works correctly first time, I assume?

Credit to JL for admitting to us that he got trapped - presumably *before* shipping this error to customers and having to fix it for them.

The board works first rev, and we're going to sell a lot of them for about 12x what they cost to make. So keep on whining!

Don't let your customer get to know that.

We really sell IP, not parts. Microsoft charges kilobucks for a

All our customers have the option to get a better deal somewhere else. One good customer has told us that we could charge more and they'd still be happy. A $5K VME module is below the noise floor to what they are building. They want performance and support.

We made a small mistake on a bunch of data acquisition cards (high-rate DMA data dumps of FIFOS caused a 20 uV input offset, rectified digital glitches) and they wanted to pay us to fix them! We never take money to fix our mistakes.

I always wondered why bench supplies don't have programmable delays so you could test things like that.

After having (one of my very few :-) chip failures due to sequencing, I added power supply sequencing to my simulation protocols.

I also do a slow slew test on the power supply ramping... had one chip that sucked enough current during a slow ramp-up that the supply choked... ruined neither chip or supply, but was a royal PITA. ...Jim Thompson

One series of Xilinx FPGAs acted as if there were farads of capacitance across the core. You had to pull Vcc_core up hard and fast.

Lots of mixed-signal parts latch up if the supplies are sequenced wrong, or one supply starts on the wrong side of zero.

Yep. Also: Even most 74HCxxx parts will crowbar the rails if VDD is ramped up slowly enough... I have resorted to what is basically a DC-coupled POR that holds logic in a frozen state until 80% of VDDmin is reached.

Yes. What you and Phil do with diodes I do (on-chip) with MOSFET's that lock off current paths until both supplies are the right polarity. ...Jim Thompson