HiSomething that I have been coming back to a number of times:When placing capacitors for decoupling of a microcontroller datasheets often suggest a 1nF/100nF and maybe a number of themBut it needs to be aligned to what is actually the load.Say I have a microcontroller running at 100MHz. Assumption (and that could be wrong), is that for the given technology the switching of the transistors are 10 times as fast, so 1nsIf the micro runs at 100mA during active state (all peripherals and core running), and it then runs a SLEEP instruction, it immediately reduces the current from 100mA to 0 in 1ns, right?If it is operated at 3.3V, using standard 2.2uF cap:(Murata, 10V, X7R)GCM21BR71A225KA37K content at 1ns is 350MHz, For the above capacitor the impedance is 0.6ohms at 350MHz. For the 100mA load shift we get 60mV transient voltage (plus a lot of ringing due to inductance not included)I would allow for a 100mV voltage transient during that load shift, so it seems this single 2.2uF cap would be enoughA discussion of the topic here:Specifically about the capacitors of today, with same package size plot comparison: 1) From that plot it makes no sense talking about a lot of different caps in parallel. One single 2.2uF rules?Adding to this, I have a PCB with about 10.000 mm2 area, where I can place a VCC and GND plane. If uninterrupted 100um distance between the planes I get 5nF of very good HF capacitor with 0.1ohm impedance at 350MHz. Again, not need for smaller caps in the designOn top of this the 100mA load in 1ns is probably a worst case situation. During normal operation the microcontroller is running, and not all transistors are switching at the same timeAbove constrained case does not take the switching capacitance of the microcontroller transistors into account.Any inputs to the above?Have anybody tried to measure the real life load of a microcontroller?RegardsKlaus

One needs of course to be careful about plane resonance as shown in figure 2 of this publication:

On Thu, 21 Oct 2021 22:35:06 +0200, Klaus Kragelund wrote:The reason there are so many bypassing theories is that almostanything works.

Microcontroller decoupling, >1uF rules?

Oct 19, 2021 Last reply: 4 years ago 21 Replies

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The problem with that thinking is that caps are very seldom connected to the chip by traces, rather by ground and power planes. I recall all manner of analysis that talked about the geometry of the three way connection of chip, cap and planes, mostly wrong analysis because it was never tested or even simulated other than in the mind.

That has been debunked. The caps are coupled to the power plane and provide bulk capacitance more so than being individual caps to the pins. A cap can be inches away before you see significant effects. This is because the power and ground planes act as transmission lines supplying the current required until the current wavefront reaches the cap and the cap provides current in the reflection. Transmission lines are not lumped inductors or capacitors and thinking of them as such produces wrong results. Most rules of thumb have never been tested and when they are tested turn out to be wrong or at least exaggerated.

Do you analyzed transmission lines by treating them as lumped inductors??? Why would you treat the transmission line formed by the power/ground plane pair as a lumped inductor between the power pin on the chip and a decoupling cap? The power/ground plane pair is not just another cap connected to your PDS, it's the transmission line connecting everything together.

Microcontroller decoupling, >1uF rules?

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