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Back to Back PMOS FETs

I'm not sure how this circuit works. The circuit is a boost for low voltage, low impedance power sources. That's fine, I understand that basically. But I asked LT about a way to shut it down and this is what they sent me, the addition of a pair of back to back PMOS FETs. The simulation does stop oscillating, but I'm not clear on how the PMOS FETs are working.

Can someone explain this? With nearly 0V between gate and source, the FETs should both be off. The point C2A swings freely. The gate voltages seem to swing with the drive at about half amplitude. I suppose that is capacitance of the gate-drain and the high impedance of the resistor R1. When the drive is 2 volts the oscillations stop.

I just can't follow what is happening. Mostly I don't understand the use of two FETs back to back. But I also don't understand the use of P channel devices when the gate drive is positive. The FETs don't actually appear to be turning on or off.

As to the switcher operation, I don't see how they can make this boost circuit work at such low voltages. The oscillations start when Vin is just 52 uV!!! How dem do dat?

Version 4 SHEET 1 3380 1564 WIRE 1120 96 816 96 WIRE 1296 96 1168 96 WIRE 1408 96 1296 96 WIRE 1440 96 1408 96 WIRE 1568 96 1504 96 WIRE 1616 96 1568 96 WIRE 2432 96 1872 96 WIRE 816 128 816 96 WIRE 1120 128 1120 96 WIRE 1168 128 1168 96 WIRE 1408 192 1408 96 WIRE 1440 192 1408 192 WIRE 1552 192 1504 192 WIRE 1584 192 1552 192 WIRE 1616 192 1584 192 WIRE 2320 192 1872 192 WIRE 1168 240 1168 208 WIRE 816 272 816 208 WIRE 832 272 816 272 WIRE 1120 288 1120 208 WIRE 1584 288 1120 288 WIRE 1616 288 1584 288 WIRE 2208 288 1872 288 WIRE 2208 304 2208 288 WIRE 816 320 816 272 WIRE 1296 368 1264 368 WIRE 1408 368 1392 368 WIRE 1424 368 1408 368 WIRE 1552 368 1552 192 WIRE 1552 368 1520 368 WIRE 1264 384 1264 368 WIRE 1616 384 1584 384 WIRE 2128 384 1872 384 WIRE 2208 384 2208 368 WIRE 1584 400 1584 384 WIRE 2128 400 2128 384 WIRE 1088 432 1024 432 WIRE 1376 432 1376 416 WIRE 1376 432 1088 432 WIRE 1440 432 1440 416 WIRE 1440 432 1376 432 WIRE 816 480 816 400 WIRE 1120 480 816 480 WIRE 1296 480 1168 480 WIRE 1408 480 1296 480 WIRE 1440 480 1408 480 WIRE 1568 480 1504 480 WIRE 1616 480 1568 480 WIRE 1936 480 1872 480 WIRE 1968 480 1936 480 WIRE 2048 480 2032 480 WIRE 2128 480 2128 464 WIRE 1120 512 1120 480 WIRE 1168 512 1168 480 WIRE 1408 576 1408 480 WIRE 1440 576 1408 576 WIRE 1552 576 1504 576 WIRE 1584 576 1552 576 WIRE 1616 576 1584 576 WIRE 1936 576 1872 576 WIRE 1968 576 1936 576 WIRE 2048 576 2032 576 WIRE 1168 624 1168 592 WIRE 1120 672 1120 592 WIRE 1584 672 1120 672 WIRE 1616 672 1584 672 WIRE 1888 672 1872 672 WIRE 1984 672 1888 672 WIRE 2000 672 1984 672 WIRE 2000 688 2000 672 WIRE 1296 752 1264 752 WIRE 1408 752 1392 752 WIRE 1424 752 1408 752 WIRE 1552 752 1552 576 WIRE 1552 752 1520 752 WIRE 1264 768 1264 752 WIRE 1616 768 1584 768 WIRE 1888 768 1888 672 WIRE 1888 768 1872 768 WIRE 2000 768 2000 752 WIRE 1584 784 1584 768 WIRE 1024 816 1024 432 WIRE 1376 816 1376 800 WIRE 1376 816 1024 816 WIRE 1440 816 1440 800 WIRE 1440 816 1376 816 WIRE 1024 832 1024 816 WIRE 1616 864 1584 864 WIRE 1888 864 1872 864 WIRE 1584 880 1584 864 WIRE 1024 928 1024 912 WIRE 1104 928 1024 928 WIRE 1168 928 1104 928 WIRE 1168 944 1168 928 WIRE 1168 1040 1168 1024 WIRE 1168 1040 1024 1040 WIRE 1024 1056 1024 1040 FLAG 1168 240 0 FLAG 1584 880 0 FLAG 1168 624 0 FLAG 832 272 0 FLAG 1888 864 0 FLAG 2000 768 0 FLAG 2048 480 0 FLAG 2048 576 0 FLAG 2128 480 0 FLAG 816 96 IN+ FLAG 816 480 IN- FLAG 2128 384 OUT FLAG 1584 400 0 FLAG 1584 784 0 FLAG 1264 384 0 FLAG 1264 768 0 FLAG 1024 1056 0 FLAG 1568 96 C1A FLAG 1584 192 C2A FLAG 1584 288 SWA FLAG 1568 480 C1B FLAG 1584 576 C2B FLAG 1584 672 SWB FLAG 1984 672 VAUX FLAG 1088 432 SW FLAG 1296 96 TA FLAG 1296 480 TB FLAG 1408 752 MIDB FLAG 1408 368 MIDA FLAG 1936 576 Vst FLAG 1936 480 VLDO FLAG 2208 384 0 FLAG 2208 288 OUT2 FLAG 1104 928 V3+ SYMBOL PowerProducts\\LTC3109 1744 480 R0 SYMATTR InstName U1 SYMBOL cap 1504 80 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL cap 1504 176 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 470p SYMBOL ind2 1104 112 R0 WINDOW 0 0 43 Right 2 WINDOW 3 1 76 Right 2 SYMATTR InstName L1

SYMATTR Type ind SYMATTR SpiceLine Rser=85m SYMBOL ind2 1184 112 M0 WINDOW 0 0 41 Right 2 WINDOW 3 0 75 Right 2 SYMATTR InstName L2 SYMATTR Value 75m SYMATTR Type ind SYMATTR SpiceLine Rser=305 SYMBOL cap 1504 464 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL cap 1504 560 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 470p SYMBOL ind2 1104 496 R0 WINDOW 0 1 41 Right 2 WINDOW 3 1 75 Right 2 SYMATTR InstName L3

SYMATTR Type ind SYMATTR SpiceLine Rser=85m SYMBOL ind2 1184 496 M0 WINDOW 0 -2 41 Right 2 WINDOW 3 1 75 Right 2 SYMATTR InstName L4 SYMATTR Value 75m SYMATTR Type ind SYMATTR SpiceLine Rser=305 SYMBOL voltage 816 112 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PWL(0 0 1 30m) SYMBOL voltage 816 416 M180 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PWL(0 0 1 30m) SYMBOL cap 1984 688 R0 SYMATTR InstName C5

SYMBOL cap 1968 496 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C6

SYMBOL cap 1968 592 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C7

SYMBOL cap 2112 400 R0 SYMATTR InstName C8

SYMBOL pmos 1296 416 R270 WINDOW 0 69 19 VRight 2 WINDOW 3 102 14 VRight 2 SYMATTR InstName Q1A SYMATTR Value DI_DMP2240UDM SYMBOL pmos 1520 416 M270 WINDOW 0 67 28 VRight 2 WINDOW 3 72 -41 Invisible 2 SYMATTR InstName Q1B SYMATTR Value DI_DMP2240UDM SYMBOL pmos 1296 800 R270 WINDOW 0 69 19 VRight 2 WINDOW 3 102 14 VRight 2 SYMATTR InstName Q2A SYMATTR Value DI_DMP2240UDM SYMBOL pmos 1520 800 M270 WINDOW 0 67 28 VRight 2 WINDOW 3 72 -41 Invisible 2 SYMATTR InstName Q2B SYMATTR Value DI_DMP2240UDM SYMBOL res 1008 816 R0 SYMATTR InstName R1 SYMATTR Value 100K SYMBOL voltage 1168 928 M0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 34 65 Left 2 SYMATTR Value PULSE(0 2 0.050) SYMATTR InstName V3 SYMBOL cap 2192 304 R0 SYMATTR InstName C9

TEXT 1144 96 Bottom 2 !K1 L1 L2 .98 TEXT 1144 480 Bottom 2 !K2 L3 L4 .98 TEXT 2096 776 Left 2 !.tran 0.051 TEXT 2040 -168 Left 2 !*SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V

2.00A 0.150ohms Diodes Inc MOSFET\n.MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24\n+ PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m\n+ IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p \n+ CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u )\n* -- Assumes default L=100U W=100U -- 
--

Rick
Reply to
rickman
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Check that the parts given aren't depletion mode FETs. If they are, that would explain how they can be on with 0 gate voltage and go off with positive gate voltage.

The back-to-backness is either because they have intrinsic diodes, or because they're supposed to work regardless of the polarity of the voltage they're shorting to ground.

I would guess a very lightly-doped depletion-mode FET that's on at 0V gate voltage, that then gets turned on harder or lighter by the oscillation.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com
Reply to
Tim Wescott

No, I covered that lesson with Joerg.

DMP2240UDM DUAL P-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR

That's why I mentioned they were MOS FETs. Depletion mode is only in JFETs, right?

It is AC, so each FET has a diode which will conduct in the reverse direction. Use two and one will always be reverse biased... ok, I got that. I still can't figure the gate drive. With the FETs reversed one will always be turned off no matter what, right? Actually, the FETs need to be off with no gate drive. Otherwise there would be no way to turn on a self powered device.

So what starts the oscillation? At least in the simulation as the input voltage slowly ramps up there is nothing until something is triggered and the internal switch opens starting the oscillation. The highest voltage I can find on the inputs to the chip is about 45 uV on the switch pin. There is no other power source to the chip.

I shortened the the time simulated to explore this so it only takes 15 seconds to run the sim.

--

Rick
Reply to
rickman

Check out...

OverAndReverseVoltageProtection.pdf

on the S.E.D/Schematics page of my website... back-to-back "bodies" provide isolation schemes with which the imaginative mind can go wild.

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Only JFETs and depletion-mode MOSFETs, at least.

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It's never out of line to suspect a typo -- the guy may not have actually run the simulation he sent you.

Noise? I dunno -- there's plenty of oscillators out there that's start up from self noise, without requiring a kick in the pants. A simple RC phase- shift oscillator would do it, as would an astable multivibrator, particularly if the designer made sure that it was intentionally unbalanced somehow.

JT probably knows the details -- I know that if you give me a device that'll show gain at 50mV, I can give you back an oscillator.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com
Reply to
Tim Wescott

You are right. They built the circuit to make sure it worked. Hey, we're talking about Linear Technology...

In the simulation it looks like a switch comes on hard at the starting point. The current into the switch pin is ramping up slowly and then

*wham* comes down to nearly zero. A simple FET of any type isn't going to switch that fast or hard. With on power on the circuit I can't figure this out. Or is it just an artifact of the simulation that is a bit simplistic from the real world?

It should only take 15 seconds to run the simulation. Care to take a look?

--

Rick
Reply to
rickman

Not necessarily, although JFETs are the commonest depletion-mode devices.

MOSFETs *can* be made in either depletion or enhancement mode, although enhancement is by far the most common. You'll occasionally see "zero-threshold" MOSFETs, which are right on the boundary between the two.

Reply to
David Platt

I ran the simulation -- it was flat line all the way across, even when I increased the simulation time from 50ms to 1s.

--
www.wescottdesign.com
Reply to
Tim Wescott

That's very symptomatic of a 2-FET astable multivibrator. The FETs are arranged in a positive feedback loop such that one FET turning on tends to turn the other one off, and visa-versa. Then the gates are capacitively coupled.

With bipolar transistors it's about the most reliable "hobbyist" noisemaker that you can come up with -- I think it was the first bread- boarded circuit I ever got to work, when I was 12 or so (not counting the paint-by-numbers Radio Shack stuff).

--
www.wescottdesign.com
Reply to
Tim Wescott

On 11/23/2014 9:19 PM, Tim Wescott wrote:

I don't know what to tell you. It runs fine for me. I didn't have to adjust anything, I just added labels to view the signals. The model for the FETs is in the schematic. Shouldn't the output of the PWL be ramping up if nothing else?

I see the point labeled IN+ ramping up and when it reached about 51 uV at time 1.7 ms the internal switch at SWA opens and the current in that pin goes from 86 uA to about 1 uA. This is when the oscillations start.

Just to make sure we are on the same page I am attaching my current copy of the file which I have open in the simulator now.

Version 4 SHEET 1 3380 1564 WIRE 1120 96 816 96 WIRE 1296 96 1168 96 WIRE 1408 96 1296 96 WIRE 1440 96 1408 96 WIRE 1568 96 1504 96 WIRE 1616 96 1568 96 WIRE 2432 96 1872 96 WIRE 816 128 816 96 WIRE 1120 128 1120 96 WIRE 1168 128 1168 96 WIRE 1408 192 1408 96 WIRE 1440 192 1408 192 WIRE 1552 192 1504 192 WIRE 1584 192 1552 192 WIRE 1616 192 1584 192 WIRE 2320 192 1872 192 WIRE 1168 240 1168 208 WIRE 816 272 816 208 WIRE 832 272 816 272 WIRE 1120 288 1120 208 WIRE 1584 288 1120 288 WIRE 1616 288 1584 288 WIRE 2208 288 1872 288 WIRE 2208 304 2208 288 WIRE 816 320 816 272 WIRE 1296 368 1264 368 WIRE 1408 368 1392 368 WIRE 1424 368 1408 368 WIRE 1552 368 1552 192 WIRE 1552 368 1520 368 WIRE 1264 384 1264 368 WIRE 1616 384 1584 384 WIRE 2128 384 1872 384 WIRE 2208 384 2208 368 WIRE 1584 400 1584 384 WIRE 2128 400 2128 384 WIRE 1088 432 1024 432 WIRE 1376 432 1376 416 WIRE 1376 432 1088 432 WIRE 1440 432 1440 416 WIRE 1440 432 1376 432 WIRE 816 480 816 400 WIRE 1120 480 816 480 WIRE 1296 480 1168 480 WIRE 1408 480 1296 480 WIRE 1440 480 1408 480 WIRE 1568 480 1504 480 WIRE 1616 480 1568 480 WIRE 1936 480 1872 480 WIRE 1968 480 1936 480 WIRE 2048 480 2032 480 WIRE 2128 480 2128 464 WIRE 1120 512 1120 480 WIRE 1168 512 1168 480 WIRE 1408 576 1408 480 WIRE 1440 576 1408 576 WIRE 1552 576 1504 576 WIRE 1584 576 1552 576 WIRE 1616 576 1584 576 WIRE 1936 576 1872 576 WIRE 1968 576 1936 576 WIRE 2048 576 2032 576 WIRE 1168 624 1168 592 WIRE 1120 672 1120 592 WIRE 1584 672 1120 672 WIRE 1616 672 1584 672 WIRE 1888 672 1872 672 WIRE 1984 672 1888 672 WIRE 2000 672 1984 672 WIRE 2000 688 2000 672 WIRE 1296 752 1264 752 WIRE 1408 752 1392 752 WIRE 1424 752 1408 752 WIRE 1552 752 1552 576 WIRE 1552 752 1520 752 WIRE 1264 768 1264 752 WIRE 1616 768 1584 768 WIRE 1888 768 1888 672 WIRE 1888 768 1872 768 WIRE 2000 768 2000 752 WIRE 1584 784 1584 768 WIRE 1024 816 1024 432 WIRE 1376 816 1376 800 WIRE 1376 816 1024 816 WIRE 1440 816 1440 800 WIRE 1440 816 1376 816 WIRE 1024 832 1024 816 WIRE 1616 864 1584 864 WIRE 1888 864 1872 864 WIRE 1584 880 1584 864 WIRE 1024 928 1024 912 WIRE 1104 928 1024 928 WIRE 1168 928 1104 928 WIRE 1168 944 1168 928 WIRE 1168 1040 1168 1024 WIRE 1168 1040 1024 1040 WIRE 1024 1056 1024 1040 FLAG 1168 240 0 FLAG 1584 880 0 FLAG 1168 624 0 FLAG 832 272 0 FLAG 1888 864 0 FLAG 2000 768 0 FLAG 2048 480 0 FLAG 2048 576 0 FLAG 2128 480 0 FLAG 816 96 IN+ FLAG 816 480 IN- FLAG 2128 384 OUT FLAG 1584 400 0 FLAG 1584 784 0 FLAG 1264 384 0 FLAG 1264 768 0 FLAG 1024 1056 0 FLAG 1568 96 C1A FLAG 1584 192 C2A FLAG 1584 288 SWA FLAG 1568 480 C1B FLAG 1584 576 C2B FLAG 1584 672 SWB FLAG 1984 672 VAUX FLAG 1088 432 SW FLAG 1296 96 TA FLAG 1296 480 TB FLAG 1408 752 MIDB FLAG 1408 368 MIDA FLAG 1936 576 Vst FLAG 1936 480 VLDO FLAG 2208 384 0 FLAG 2208 288 OUT2 FLAG 1104 928 V3+ SYMBOL PowerProducts\\LTC3109 1744 480 R0 SYMATTR InstName U1 SYMBOL cap 1504 80 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL cap 1504 176 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 470p SYMBOL ind2 1104 112 R0 WINDOW 0 0 43 Right 2 WINDOW 3 1 76 Right 2 SYMATTR InstName L1

SYMATTR Type ind SYMATTR SpiceLine Rser=85m SYMBOL ind2 1184 112 M0 WINDOW 0 0 41 Right 2 WINDOW 3 0 75 Right 2 SYMATTR InstName L2 SYMATTR Value 75m SYMATTR Type ind SYMATTR SpiceLine Rser=305 SYMBOL cap 1504 464 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL cap 1504 560 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 470p SYMBOL ind2 1104 496 R0 WINDOW 0 1 41 Right 2 WINDOW 3 1 75 Right 2 SYMATTR InstName L3

SYMATTR Type ind SYMATTR SpiceLine Rser=85m SYMBOL ind2 1184 496 M0 WINDOW 0 -2 41 Right 2 WINDOW 3 1 75 Right 2 SYMATTR InstName L4 SYMATTR Value 75m SYMATTR Type ind SYMATTR SpiceLine Rser=305 SYMBOL voltage 816 112 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PWL(0 0 1 30m) SYMBOL voltage 816 416 M180 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PWL(0 0 1 30m) SYMBOL cap 1984 688 R0 SYMATTR InstName C5

SYMBOL cap 1968 496 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C6

SYMBOL cap 1968 592 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C7

SYMBOL cap 2112 400 R0 SYMATTR InstName C8

SYMBOL pmos 1296 416 R270 WINDOW 0 69 19 VRight 2 WINDOW 3 102 14 VRight 2 SYMATTR InstName Q1A SYMATTR Value DI_DMP2240UDM SYMBOL pmos 1520 416 M270 WINDOW 0 67 28 VRight 2 WINDOW 3 72 -41 Invisible 2 SYMATTR InstName Q1B SYMATTR Value DI_DMP2240UDM SYMBOL pmos 1296 800 R270 WINDOW 0 69 19 VRight 2 WINDOW 3 102 14 VRight 2 SYMATTR InstName Q2A SYMATTR Value DI_DMP2240UDM SYMBOL pmos 1520 800 M270 WINDOW 0 67 28 VRight 2 WINDOW 3 72 -41 Invisible 2 SYMATTR InstName Q2B SYMATTR Value DI_DMP2240UDM SYMBOL res 1008 816 R0 SYMATTR InstName R1 SYMATTR Value 100K SYMBOL voltage 1168 928 M0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 34 65 Left 2 SYMATTR Value PULSE(0 2 0.050) SYMATTR InstName V3 SYMBOL cap 2192 304 R0 SYMATTR InstName C9

TEXT 1144 96 Bottom 2 !K1 L1 L2 .98 TEXT 1144 480 Bottom 2 !K2 L3 L4 .98 TEXT 2096 776 Left 2 !.tran 0.051 TEXT 2040 -168 Left 2 !*SRC=DMP2240UDM;DI_DMP2240UDM;MOSFETs Enh;20.0V

2.00A 0.150ohms Diodes Inc MOSFET\n.MODEL DI_DMP2240UDM PMOS( LEVEL=1 VTO=1.00 KP=11.9u GAMMA=1.24\n+ PHI=.75 LAMBDA=514u RD=21.0m RS=21.0m\n+ IS=1.00p PB=0.800 MJ=0.460 CBD=81.1p \n+ CBS=97.4p CGSO=720n CGDO=600n CGBO=1.88u )\n* -- Assumes default L=100U W=100U -- 
--

Rick
Reply to
rickman

Yeah, I've seen those a million times. It's the same circuit as a FF, but with capacitors making it not stable in either mode.

I guess I'm just surprised it starts with no power supply. Sure the multivibrator will start up on it's own, but with 50 uV for a power source?

I guess part of why I am surprised at this is because this is the only part I could find for getting power from very low voltage TEGs which will start below some 300 mV, a *lot* below 300 mV. Any idea what the tradeoff is?

--

Rick
Reply to
rickman

Still doesn't work. I see that Vin1 and Vin2 are grounded, which seems wrong -- is that the case on yours? Could the library part be different between our two LTSpices?

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com
Reply to
Tim Wescott

I know. LT provided this design. The only change I made was to add labels to every wire so I could probe it. The design is intended to work with one TEG with polarity reversing. Instead they used two voltage sources and grounded the Vin pins. The circuit with a bipolar TEG works by one or the other input circuit being active. With the two TEGs both run at once.

I changed the circuit to one TEG to test it with both polarities of the input. The circuit still works, but the shutdown FETs don't. I had a problem with the simulation working so I added a 100Meg resistor from IN- to ground. Otherwise it is exactly the circuit shown in the data sheet for this mode.

It is hard to have any idea what exactly is happening because in their block diagram of the chip, this part of the circuit is contained in a black box labeled "Power Switches" including the VinA and VinB pins. I am guessing the VinA is connected to SWA via a FET switch and does not otherwise connect to the rest of the circuit. That might explain why the simulation won't run without the resistor. Their behavioral model likely uses something like a voltage controlled switch that is totally isolated. Grounding the two Vin pins in the original schematic would close the loop for each separate input circuit, but that can't be done in the bipolar TEG circuit.

I'm not sure what to do about the shutdown FETs. I didn't understand how they were supposed to be working in the first place, so it would be hard to figure out why they don't work now.

--

Rick
Reply to
rickman

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