integrated circuit modeling with LTSpice

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It is my understanding that during transient analysis, the smallest step size is proportional to how long you look, like 1/200th. Unless something really interesting happens, then the steps will get shorter. But, DON'T get shorter UNLESS something interesting happens.

For example 0 to 1 sec has fairly large steps compared to 0 to 10 uS, which means the analyses probably 'stepped' over your circuit's instability.

You can confirm this by adding to your transient command largest step is 1nS and see what happens.

Also, watch out for LTspice adding default physical values to your components.Like resistance added to inductance, etc. It is my understanding that PSpice does NOT do this. You can remove default additions by specifically asking at each component.

Ok, I got responses to a couple of things that were ancillary to the thrust of my post. It boils down to: Are there ready-made resources for using LTSpice in CMOS modeling

Crickets or gnats or just a pain-in-the-ass to use ?:-)

I find Virtuoso to be very difficult to use. Last Fall I had occasion to be working a project (as designer) with a Cadence group doing the overall system modeling. It was with great joy for me to rub their noses in the fact that PSpice ran circles around the Cadence tool set for speed and could easily model things that the Cadence team struggled to model as "wreal".

Fortunately the guy across the conference table from me was a fellow MIT graduate, so they took (and gave) criticism graciously (unlike many posters here :-)

Level=1 is crap. Why aren't you using a BSIM model?

Cgdmax and Cgdmin aren't Spice parameters. They may exist in LTspice (?), but LTspice does lots of things that are not Berkeley-Spice compliant.

Since you have the Cadence tool set, can't you read the device model library? LTspice _does_ recognize BSIM3xx models.

That's probably failure to set max time-step properly. Read the LTspice help and put all your Control Panel settings to "conventional" Spice, no convergence short-cuts (LTspice is optimized for switcher design, not chips).

You might post an LTspice schematic so that we know what you are trying to do. ...Jim Thompson

Since he's in an educational environment, it's not uncommon that while Cadence provides their software for free or nearly-free, it comes with no support or support limited only to instructors (and many an instructor finds it easier to say, "well... why don't you just go use LTspice?" than to actually pursue the real problem). Additionally, in educational environments, even if you find a patch or service pack, it can take a fair amount of time and effort to get the IT guys to actually install it. (E.g., some institutes only perform software updates on a strict quarterly schedule -- critical bugs be damned!)

Or the "professor" has the one license tied up doing his private consulting project. ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

All right thanks, now I'm getting some information I can actually use. In outline, my project is to improve the speed of a charge pump that one of our professors patented some years ago. You can see the patent if you go to google patents and type in 7583116. Here is a LTSpice netlist I threw together for his charge pump circuit's topology. Mine will be a bit different, but I'm posting the original. As I recall, after putting in the "miller" cap to stabilize it, the original circuit ran (switched) at 100 MHz. Because I've only been able to come up with a very crappy model for the mosfets so far, I had to use much slower switching in the simulation. I'm attaching an LTSpice netlist for the basic topology of the circuit in the patent below if for some reason anyone wants to play with it. All the nmos are identical. I have one pair of mosfets doubled up, where in the original patent you'll see a single mosfet with twice the aspect ratio of the others. I also don't include a high-side current source, which is essentially a mirror image of the one you see.

Version 4 SHEET 1 1788 680 WIRE 352 -256 256 -256 WIRE 368 -256 352 -256 WIRE 560 -256 368 -256 WIRE 576 -256 560 -256 WIRE 768 -256 576 -256 WIRE 784 -256 768 -256 WIRE 976 -256 784 -256 WIRE 1184 -256 976 -256 WIRE 1200 -256 1184 -256 WIRE 688 -192 496 -192 WIRE 1104 -192 688 -192 WIRE 368 -176 368 -256 WIRE 560 -176 560 -256 WIRE 432 -160 416 -160 WIRE 496 -160 496 -192 WIRE 496 -160 432 -160 WIRE 512 -160 496 -160 WIRE 768 -160 768 -256 WIRE 1184 -160 1184 -256 WIRE 688 -144 688 -192 WIRE 720 -144 688 -144 WIRE 1104 -144 1104 -192 WIRE 1136 -144 1104 -144 WIRE 352 -128 352 -256 WIRE 368 -128 352 -128 WIRE 576 -128 576 -256 WIRE 576 -128 560 -128 WIRE 784 -112 784 -256 WIRE 784 -112 768 -112 WIRE 1200 -112 1200 -256 WIRE 1200 -112 1184 -112 WIRE 432 -80 432 -160 WIRE 432 -80 368 -80 WIRE 976 -48 976 -256 WIRE 368 -32 368 -80 WIRE 368 -32 288 -32 WIRE 368 -16 368 -32 WIRE 976 0 912 0 WIRE 1120 32 1024 32 WIRE 1184 32 1184 -64 WIRE 1184 32 1120 32 WIRE 288 64 288 -32 WIRE 320 64 288 64 WIRE 976 80 976 48 WIRE 992 128 976 128 WIRE 1184 128 1184 32 WIRE 928 160 -64 160 WIRE 1200 176 1184 176 WIRE 256 208 256 -256 WIRE 560 208 560 -80 WIRE 624 208 560 208 WIRE 768 208 768 -64 WIRE 1136 208 768 208 WIRE 560 224 560 208 WIRE 768 224 768 208 WIRE -64 272 -64 160 WIRE 560 272 544 272 WIRE 784 272 768 272 WIRE 624 304 624 208 WIRE 624 304 608 304 WIRE 720 304 624 304 WIRE 368 320 368 80 WIRE 368 320 320 320 WIRE 368 352 368 320 WIRE 560 352 560 320 WIRE 768 352 768 320 WIRE 976 352 976 176 WIRE 976 352 768 352 WIRE 128 384 0 384 WIRE 384 400 368 400 WIRE 544 400 544 272 WIRE 560 400 544 400 WIRE 784 400 784 272 WIRE 784 400 768 400 WIRE 992 400 992 128 WIRE 992 400 976 400 WIRE 1120 400 1120 32 WIRE 320 432 320 320 WIRE 624 432 624 304 WIRE 624 432 608 432 WIRE 720 432 624 432 WIRE 1152 448 1120 448 WIRE 720 464 720 432 WIRE 928 464 928 432 WIRE 928 464 720 464 WIRE 128 480 128 384 WIRE 1072 480 128 480 WIRE -64 512 -64 352 WIRE 0 512 0 464 WIRE 0 512 -64 512 WIRE 256 512 256 288 WIRE 256 512 0 512 WIRE 304 512 256 512 WIRE 368 512 368 448 WIRE 368 512 304 512 WIRE 384 512 384 400 WIRE 384 512 368 512 WIRE 544 512 544 400 WIRE 544 512 384 512 WIRE 560 512 560 448 WIRE 560 512 544 512 WIRE 768 512 768 448 WIRE 768 512 560 512 WIRE 784 512 784 400 WIRE 784 512 768 512 WIRE 912 512 912 0 WIRE 912 512 784 512 WIRE 976 512 976 448 WIRE 976 512 912 512 WIRE 992 512 992 400 WIRE 992 512 976 512 WIRE 1120 512 1120 496 WIRE 1120 512 992 512 WIRE 1152 512 1152 448 WIRE 1152 512 1120 512 WIRE 1184 512 1184 224 WIRE 1184 512 1152 512 WIRE 1200 512 1200 176 WIRE 1200 512 1184 512 FLAG 304 512 0 SYMBOL pmos4 416 -80 R180 SYMATTR InstName M1 SYMBOL nmos4 608 224 M0 SYMATTR InstName M2 SYMBOL voltage 256 192 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 1 SYMBOL nmos4 608 352 M0 SYMATTR InstName M3 SYMBOL pmos4 512 -80 M180 SYMATTR InstName M4 SYMBOL nmos4 320 352 R0 SYMATTR InstName M5 SYMBOL nmos4 720 224 R0 SYMATTR InstName M6 SYMBOL nmos4 720 352 R0 SYMATTR InstName M7 SYMBOL nmos4 928 352 R0 SYMATTR InstName M9 SYMBOL pmos4 720 -64 M180 SYMATTR InstName M10 SYMBOL nmos4 1136 128 R0 SYMATTR InstName M11 SYMBOL pmos4 1136 -64 M180 SYMATTR InstName M13 SYMBOL nmos4 1024 -48 M0 SYMATTR InstName M14 SYMBOL voltage -64 256 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(0 1 0 10n 10n 1u 2u) SYMBOL nmos4 1072 400 R0 SYMATTR InstName M12 SYMBOL nmos4 928 80 R0 SYMATTR InstName M15 SYMBOL voltage 0 368 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(1 0 0 10n 10n 1u 2u) SYMBOL nmos4 320 -16 R0 SYMATTR InstName M8

(1) I see no dimensions on the MOS devices.

(2) What process? I have models from many foundries. Maybe I have the one you need.

(3) Or send me the models from your Cadence libraries. ...Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

I had spice directives on the schematic. I didn't think they would be much use so I deleted them before I posted the netlist. But here they are

.model PMOS PMOS(Level=1 Gamma=.2673 Tox=8n Phi=.33 Rs=.01 Kp=.065 Vto=-0.4 Lambda=.05 Rd=.01 Cbd=.009p Cbs=.027p Pb=0.7 Is=10f N=1)

.model NMOS NMOS(Level=1 Gamma=.0945 Tox=8n Phi=.385 Rs=.01 Kp=.15 Vto=0.3 Lambda=.05 Rd=.01 Cbd=.009p Cbs=.027p Pb=0.7 Is=10f N=1)

It was a process IBM was using in the nineties, but I don't have to use the original process. I just want something that works.

I'd like to send you more information, but I couldn't get through the email icon on your website. Is there any way I can send you email from my school account? It is mrobins2 at uvm.edu

That is a "model", not dimensions

I have bucket-loads of IBM models, having designed the first Garmin chip on an IBM process (Burlington, VT).

I'll send you an E-mail. ...Jim Thompson

You are correct. Spice picks the time and then curve fits the output to fit on your time grid unless you make the effort to specify the time step. For circuit analysis where timing is critical, you need the max time step parameter. This also effects THD calculations.

The LTSpice symbol you used needs dimensions, not a .model. Try right clicking on each symbol to see what I mean.

I can put dimensions in that dialog box, in fact I tried doing it that way, but then the circuit had infinite bandwidth. Perfect step response up in the terahertz or something. No way around using a model for the parasitics. And of course there's also body effect.

The three-terminal NMOS symbol takes a .model. Alternatively you could (like I did) make a new "subckt NMOS" symbol that is really an "X", and takes a subcircuit that you provide. A lot of manufacturers devices have subcircuit models, I originally did it to replicate Jim's 2N7000 model comparisons of eons ago.