LDO question

Hi Jutek,

Im no expert but I can try to explain...

LDO DC gain is made up of three parts: gain of the error amplifier gain of the pass transistor gain and "gain" (or rather attenuation) of the resistor divider. The error amplifier and the resistor divider are non inverting, the PMOS pass transistor is inverting.

gain of resistor divider = + R2 / (R1+R2) gain of pass transistor (pass) = - gm_pass * (ro_pass || Rload || (R1+R2) ) gain of error amp (ea) = + gm_ea * Rout_ea

Multiply these three terms to get the total open loop DC gain.

The reason the gain of the pass transistor is what it is, is because in an ldo the pass transistor is connected in common source configuration, with input at the gate and output at the drain. (This fact is also the source of all ldo stability problems)

(note that gm_pass depends on current through the pass transistor which is basically the load of the ldo, so open loop gain changes with load)

Next about the location of poles and the loop stability...

A basic LDO configuration introduces two (not very high frequency) poles, which result in the loop gain crossing 0db at -40db/dec slope and thus causing instability.

The first pole is because of the load capacitance. One can imagine that as frequency increases the load capacitance will act more and more like a short circuit thus causing the gain to roll off. This pole occurs at quite a low frequency usually because the load cap is quite large.

Frequency of Pole 1 = 1/[ (ro_par || (R1+R2) || RL)*(CL) ]

The second pole is due to Miller effect at the pass transistor. Since there is (inverting) gain between the gate of the pass transistor and the drain, the Cgd capacitor of the pass transistor will appear as a much bigger capacitor from gate to ac ground:

Cgd_miller = Cgd*(dc gain of pass transistor )

Cgd_miller = Cgd*(gm_pass)*(ro_pass || (R1+R2) || RL)

Total capacitance from gate to small signal ground will be:

Ceffective = Cgd_miller + Cgs

This large capacitance gives another mid frequency pole at:

Frequency of Pole 2 = 1/ (Rpar*Ceffective)

(Rpar is the resistance at the output of the error amp that is doing the correction)

To avoid the problem caused by 2 poles, a zero is usually introduced by adding a small resistance in series with the output capacitor (or use a high esr capacitor).

Frequency of zero = 1/(Resr*CL)

This zero will change the roll off back to -20db/dec and result in stability. Note that both poles and dc gain depend on "gm_pass" which in turn depends on load current, so the ldo can be stable only over a particular range of load currents. simulate all cases of load

To answer your question, it will depend on:

1. how much power dissipation you need the ldo to handle in the worst case.
2. how much dc open loop gain you need.

then the size should be tweaked to maintain stability....

Thanks qq

jutek wrote:

Hi Jutek,

I dont get exactly what you mean. Can you rephrase?

Thanks qq

jutek wrote:

By gain less than one..do you mean gain is negative?...if so that is normal as the pmos is inverting. But if you mean that the magnitude of gain is between zero and one then that is not possible. The modulus of the gain has to be greater than one. The rds has nothing to do with it. Make sure you have some load at the output in your simulations. are you doing an ac sweep? what options are you giving. you could post some netlist to show how you are measuring this gain

The load cap is needed to improve the transient response. Imagine if the output current suddenly changes from 1ma to 10ma. The ldo will need some reactin time to supply this now increased load. In the time taken for the ldo to react, the voltage at the output will drop. So you need a cap which can supply the current during the short instant of time while the loop reacts - so that the output voltage can be kept stable.

you mean like a source follower? I am not sure about this, i think It will push the second pole to a higher frequency but I dont know if there are other issues with this.

Thanks qq

thank You very much for the clear explanation

best regards

luke

one more strange thing i met

when i use PMOS hspice model i don't have pmos gain gm=35m gds=1.7 Rl=12 or Rl=1.2k. why it's happening.

i replaced this model by voltage dependent current source and rds. i set transconductance and rds and i have the gain.

the problem is when i start to transistor level design. what then? maybe PMOS model is wrong

i mean, when i use huge PMOS (w/l=1k or more) the gain is less than 1 but i think it's connected with small rds then.

one more question. what would be if i don't use cload capictor? one pole and zero would disappear and no problem with unstability.

everyone writes, the zero is needed to compensation.

the other way. supose i use cload with esr. then i have one pole and one zero connected with it. and also one pole from opamp's output and pmos input. what if i use a buffer to lower opamp's output resistance? then, the pole will go to higher frequencies and also no problem of unstability.

regards

no i mean gain less one. i use W/L=5k gm=36m and gds=200m so according to what you wrote Pmos_gain=gm*(ro_pass || Rload ||(R1+R2) ) =36m*(5||1.2k||30k)=0.18 => -14.89dB