little homebrew LDO regulator

Good grief! Look at this!

16 ICs, 11 mosfets, 7 inductors, at least 100 other parts... to power an FPGA!

John

Do you have a book, "America's Favorite Cliches" or something?

John

On Mon, 12 Sep 2011 09:01:57 -0700, John Larkin wrote:

Try this rework using ON and Zetex supplied models. You'll need the "subckt_nmos" symbol, attached, for the FET. AFAIK, LT don't provide one.

The approx 120mV spikes on the output with 1A pulse loading appear to be due to FET stored gate charge.

Watch the long lines in the subcircuits. Turn off wrapping.

Version 4 SHEET 1 1120 680 WIRE 144 -176 32 -176 WIRE 608 -176 416 -176 WIRE 144 -144 144 -176 WIRE 608 -112 608 -176 WIRE 416 -48 416 -176 WIRE 144 -32 144 -64 WIRE 32 0 32 -176 WIRE 608 0 608 -32 WIRE 0 16 -32 16 WIRE 144 32 64 32 WIRE 192 32 144 32 WIRE 224 32 192 32 WIRE 368 32 304 32 WIRE -144 48 -208 48 WIRE 0 48 -144 48 WIRE 32 80 32 64 WIRE -208 96 -208 48 WIRE -32 144 -32 16 WIRE 80 144 -32 144 WIRE 144 144 144 96 WIRE 144 144 80 144 WIRE 224 144 144 144 WIRE 416 144 416 48 WIRE 416 144 304 144 WIRE 512 144 416 144 WIRE 704 144 512 144 WIRE 416 176 416 144 WIRE 512 176 512 144 WIRE 704 192 704 144 WIRE -208 208 -208 176 WIRE 512 272 512 240 WIRE 416 288 416 240 WIRE 512 384 512 352 WIRE 704 384 704 272 FLAG 144 -32 0 FLAG 32 80 0 FLAG -208 208 0 FLAG 416 288 0 FLAG 608 0 0 FLAG 512 384 0 FLAG 704 144 OUT FLAG -144 48 IN FLAG 192 32 AMP FLAG 80 144 FB FLAG 704 384 0 SYMBOL cap 400 176 R0 SYMATTR InstName C1 SYMATTR Value 3u SYMBOL cap 496 176 R0 SYMATTR InstName C2 SYMATTR Value 10u SYMBOL cap 128 32 R0 WINDOW 0 49 42 Left 0 WINDOW 3 50 73 Left 0 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL res 320 16 R90 WINDOW 0 -45 59 VBottom 0 WINDOW 3 -36 60 VTop 0 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL res 320 128 R90 WINDOW 0 72 52 VBottom 0 WINDOW 3 78 52 VTop 0 SYMATTR InstName R2 SYMATTR Value 10K SYMBOL voltage 608 -128 R0 WINDOW 0 55 39 Left 0 WINDOW 3 53 82 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 1.5 SYMBOL voltage -208 80 R0 WINDOW 3 44 56 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 1.15 100m 1u 10n) SYMATTR InstName V2 SYMBOL voltage 144 -160 R0 WINDOW 0 61 23 Left 0 WINDOW 3 60 60 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 12 SYMBOL res 496 256 R0 WINDOW 0 47 62 Left 0 WINDOW 3 41 98 Left 0 SYMATTR InstName R4 SYMATTR Value 0.05 SYMBOL current 704 192 R0 WINDOW 3 40 40 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 24 98 Left 0 SYMATTR Value PULSE(.1 1 0 10n 10n .5 1) SYMATTR SpiceLine load SYMATTR InstName I1 SYMBOL Opamps\\opamp2 32 -32 R0 WINDOW 3 -87 -22 Left 0 SYMATTR Value MC33071#0 SYMATTR InstName U1 SYMBOL subckt_nmos 368 -48 R0 SYMATTR InstName U2 SYMATTR Value ZXMN2A02X8 TEXT 384 408 Left 0 !.tran 5 startup TEXT -456 -136 Left 0 ;TEM2 LDO REGULATORS TEXT -416 -88 Left 0 ;JL Sep 12 2011 TEXT -168 232 Left 0 !*Zetex ZXMN2A02X8 Spice Model v1.0 Last Revised

22/2/05\n*\n.SUBCKT ZXMN2A02X8 30 40 50\n*---connections---D-G-S\nM1 6 2 7 7 Nmod L=1.16E-6 W=2.3\nM2 7 2 7 6 Pmod L=1.3E-6 W=1.3\nRG 4 2 1\nRIN 2 5 1E12\nRD 3 6 Rdmod 0.0045\nRS 7 5 Rdmod 0.01\nRL 3 5 3E9\nC1 2 5 10E-12\nC2 3 2 5E-12\nD1 5 3 Dbodymod\nLD 3 30 1.5E-9\nLG 4 40 1.0E-9\nLS 5 50 1.0E-9\n.MODEL Nmod NMOS (LEVEL=3 TOX=4.5E-8 NSUB=10E16\n+VTO=1.365 KP=3.6E-5 NFS=2E11 KAPPA=0.1 UO=650 IS=1E-15 N=10)\n.MODEL Pmod PMOS (LEVEL=3 TOX=4.5E-8 NSUB=1.5E16\n+TPG=-1 IS=1E-15 N=10)\n.MODEL Dbodymod D (IS=2E-11 RS=.015 XTI=1.5 TRS1=1.5e-3 TT=7e-9\n+CJO=450e-12 BV=22)\n.MODEL Rdmod RES (TC1=3e-3 TC2=6E-6)\n.ENDS\n* TEXT 432 48 Left 0 ;Nearest to ZXMN2A04DN8 Dual SO8 TEXT -440 232 Left 0 !.SUBCKT MC33071#0 1 2 3 4 5\n*\nC1 11 12 8.660E-12\nC2 6 7 8.000E-12\nCEE 10 99 1.231E-12\nDC 5 53 DX\nDE 54 5 DX\nDLP 90 91 DX\nDLN 92 90 DX\nDP 4 3 DX\nEGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5\nFB 7 99 POLY(5) VB VC VE VLP VLN 0 8.842E6\n+ -9E6 9E6 9E6 -9E6\nGA 6 0 11 12 251.3E-6\nGCM 0 6 10 99 3.550E-9\nIEE 3 10 DC 120.2E-6\nHLIM 90 0 VLIM 1K\nQ1 11 2 13 QX\nQ2 12 1 14 QX\nR2 6 9 100.0E3\nRC1 4 11 3.979E3\nRC2 4 12 3.979E3\nRE1 13 10 3.542E3\nRE2 14 10 3.542E3\nREE 10 99 1.664E6\nRO1 8 5 30\nRO2 7 99 45\nRP 3 4 34.09E3\nVB 9 0 DC 0\nVC 3 53 DC 1\nVE 54 4 DC .3\nVLIM 7 8 DC 0\nVLP 91 0 DC 30\nVLN 0 92 DC 30\n.MODEL DX D(IS=800.0E-18)\n.MODEL QX PNP(IS=800.0E-18 BF=600)\n.ENDS TEXT -168 -32 Left 0 ;ON Semi supplied model for MC33072 TEXT -408 -56 Left 0 ;Rework by FA Sep 14 2011

-------------------------------------------------

Save as /lib/sym/subckt_nmos.asy :-

Version 4 SymbolType CELL LINE Normal 48 48 48 96 LINE Normal 16 80 48 80 LINE Normal 40 48 48 48 LINE Normal 16 48 40 44 LINE Normal 16 48 40 52 LINE Normal 40 44 40 52 LINE Normal 16 8 16 24 LINE Normal 16 40 16 56 LINE Normal 16 72 16 88 LINE Normal 0 80 8 80 LINE Normal 8 16 8 80 LINE Normal 48 16 16 16 LINE Normal 48 0 48 16 WINDOW 0 56 32 Left 0 WINDOW 3 56 72 Left 0 SYMATTR Value NMOS SYMATTR Prefix XM PIN 48 0 NONE 0 PINATTR PinName D PINATTR SpiceOrder 1 PIN 0 80 NONE 0 PINATTR PinName G PINATTR SpiceOrder 2 PIN 48 96 NONE 0 PINATTR PinName S PINATTR SpiceOrder 3

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

Oh, good grief! Perhaps Xilinx is behind it.

LT Spice barfs all over that one!

John

It runs here. Did you install the subcircuit FET symbol? The standard one won't work with anything except "vanilla" models.

There are two files in there.

I just tried cut-'n'-paste from the downloaded copy on my newsreader. It runs fine.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

Assuming nothing blows up during sequencing, isn't it better just to use a power supply supervisory scheme? Wait for the Kosher moment, then reset everything to a known state.

When you design the error amp in a chip, it is usually one stage, simply to have less poles. So my phrasing wasn't the greatest. Gain is OK, but phase shift is bad. Since the load is reactive, you have plenty of phase shift to worry about due to load interaction, so you don't need the amp itself to contribute phase shift.

Gain gets you voltage accuracy, but you really don't need microvolt accuracy on a power supply. Rather you want things well behaved.

I've done voltage regulation internal to chips that aren't all that well regulated, generally over temp, but have great supply rejection. Making a part work well with crappy bypass wins customers.

I've always had problems driving a mosfet directly or indirectly via a gate R with an op-amp+feed back. It seems that most common op-amps suited, just do not have the output drive required to get the fet into position quick enough due to gate C which ends up with a short burst of relaxation type of oscillation. Some times it just oscillates indefinitely.

if you put a (D) derivative circuit in the feed back it seems to avoid the oscillation but then, slows down response time. If that is ok then I guess there is no issues.

What I did, just because I needed a way of getting a low ohmic path that I could maintain with fast response, I put a complemary pair of followers on the output of the op-amp I was using, as a gate driver to over come the gate C..

It seem to work even though I wouldn't recommend it as a common practice. The charge on the gate actually helped to cover up the cross over distortion.

Just my 2-CENTS. Jamie

I do have a POR chip, STM1818T, on the 3.3 volt rail. It waits a couple hundred ms after the 3.3 comes up and then releases the RESET line.

John

I think it is because of the \n escape sequence embedded therein. I had the same problem. This happens when the model is contained in the schematic rather than included from a file and the text is pasted into a text editor. I think.

John S

That's correct. Also the Greek mu UTF-8 characters can cause problems cut-'n'-paste. Better to use lower-case "u".

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)