little homebrew LDO regulator

I think operating from a higher voltage for the op amp disqualifies the design as LDO, not that I have an issue with it. You do have to make sure that as you start up (ramp the supply), there is no overshoot on the op amp.

The p-fet pass device is a variable resistor whose resistance is set by the VGS maintained by the loop. It is kind of ugly, which is why your scheme should be better. Less bad stuff can happen with a source follower, especially if it has a lot of transconductance. Again a cap to hold the gate voltage may prove useful for operation beyond the op amp bandwidth. Too big of a cap and you ruin the mid frequency control.

The worst LDO is the PNP pass device. They start to draw current as you get near saturation. All designs have some anti-saturation trick to keep the pass device out of saturation, but they do use current. Also, the anti-sat circuit is in itself another feedback loop, so stability can be tricky at very low dropout. The p-fet pass device design is better in this respect.

You find the PNP pass design in a lot of SMPS chips that bootstrap the internal voltage. Generally it is easier to design a high voltage regulator on a bicmos process if you use the PNP.

For my home brew board level projects, I always spend the extra pennies and get a p-fet LDO, usually from TI. Digikey carries them. I doubt cost conscious designs use anything but cheap ass 3 pin bipolar regulators.

LDOs as a stand alone product need over current protection. You can't have a customer poking around with a scope probe in the development phase fry a chip and expect to maintain that customer or get a new design win. The customer loses confidence in the product and thus the company. In your case, the upstream current is regulated and you are selling the final product. If you don't blow up the fet with a short, I don't think anyone else will. Basically it is a different design mentality.

The crowbar is good if someone yanks the pin with a source higher than the target voltage. Many LDOs don't provide a crowbar since that is a less likely (though not impossible) failure mechanism.

At some point you need to decide am I making a circuit for on-board use or a stand alone product. I really don't see anything wrong with this design for an on-board use.

=A0 =A0...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 |

Seems to me with a source follower or n-fet in triode, you know the power up sequence in that part of the chain. It is follow the leader.

Sickness. ...Jim Thompson

--
                  [On the Road, in New York]

| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
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| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
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I love to cook with wine.     Sometimes I even put it in the food.

I didn't mean that YOU should use the LTC3025, I meant that I didn't see the point in *it*, particularly as shown in the typical circuit.

--
If that's the case, then I'm surprised that you didn't evaluate the
"loop dynamics" with the reference voltage starting at 0V and then
rising to its terminal voltage, since that's what happens in the real
world.

It certainly changes both the turn-on and turn-off delays and the
shapes of the leading and trailing edges of the output waveform.

So, in other words, you either made a mistake or you cheated.


Also, by not specifying Trise and Tfall for V2, LTspice defaulted you
to 20µs in both instances.

Was that part of your plan?

Larkin cheated ;-)

Of course it was. Larkin has no clue as to how to evaluate stability during turn-on.

...Jim Thompson

--
                  [On the Road, in New York]

| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

Generally high gain in the error amp isn't a good idea. You don't need that kind of accuracy.

That only happens at powerup, so doesn't matter much. What I don't want is the loop to ring or oscillate, or to have terrible load regulation. We're planning to instrument the FPGA on our eval board to see if the PCIe section, which needs 1.2 volts, draws big current steps.

What are you talking about? The steps show the loop response. They allow the feedback RC to be tuned for nice damping.

The 20 us does mask the step response a little. With a 1 us input step, the output rise time is around 3 us. The optimum damping values are the same. I wish LT Spice wouldn't do that. Other simulators that I've used make a step in one sim delta-t if you specify zero rise time.

(Cue whining)

John S kindly added a load step circuit, which I should have done myself, before I posted the circuit.

It's electronics, so obviously you don't care.

It's an electronics discussion group, and it's something to discuss. Why would anyone post anything here if, as you suggest, they should work alone and do everything themselves?

Voltage regulators are a big part of the lives of most people who design electronics. How did you get to be such a grouch?

Hey, start an electronics thread yourself, once in a while, instead of lurking and bitching. That's all you and JT do any more.

John

Opamps come with high gain. I could reduce the error amp gain with another resistor, but why?

John

John -

I made some changes to your netlist on my own without knowing if they are reasonable.

1. Changed C3 to 47pF.

1. Changed C1 to 1pF (essentially zero).

2. Changed C2 to 1nF.

1. I made the load switch transition from 1meg to 1ohm in 1us. I thought that might be more reasonable. Don't know.

In LTSpice it looks okay except for the load transients at the leading and trailing edges and they are nasty.

However, I hope this helps some.

Cheers, John

Version 4 SHEET 1 1360 680 WIRE 144 -176 32 -176 WIRE 608 -176 416 -176 WIRE 144 -144 144 -176 WIRE 608 -112 608 -176 WIRE 416 -48 416 -176 WIRE 144 -32 144 -64 WIRE 32 0 32 -176 WIRE 608 0 608 -32 WIRE 0 16 -32 16 WIRE 144 32 64 32 WIRE 192 32 144 32 WIRE 224 32 192 32 WIRE 368 32 304 32 WIRE -144 48 -208 48 WIRE 0 48 -144 48 WIRE 32 80 32 64 WIRE -208 96 -208 48 WIRE -32 144 -32 16 WIRE 80 144 -32 144 WIRE 144 144 144 96 WIRE 144 144 80 144 WIRE 224 144 144 144 WIRE 336 144 304 144 WIRE 416 144 416 48 WIRE 416 144 336 144 WIRE 512 144 416 144 WIRE 608 144 512 144 WIRE 416 176 416 144 WIRE 512 176 512 144 WIRE 608 176 608 144 WIRE 336 192 336 144 WIRE -208 208 -208 176 WIRE 512 272 512 240 WIRE 416 288 416 240 WIRE 608 288 608 256 WIRE 688 288 608 288 WIRE 336 304 336 272 WIRE 688 304 688 288 WIRE 848 320 736 320 WIRE 848 336 848 320 WIRE 768 368 736 368 WIRE 512 384 512 352 WIRE 768 384 768 368 WIRE 688 400 688 384 WIRE 848 448 848 416 FLAG 144 -32 0 FLAG 32 80 0 FLAG -208 208 0 FLAG 416 288 0 FLAG 608 0 0 FLAG 512 384 0 FLAG 688 400 0 FLAG 608 144 OUT FLAG -144 48 IN FLAG 192 32 AMP FLAG 80 144 FB FLAG 336 304 0 FLAG 848 448 0 FLAG 768 384 0 SYMBOL cap 400 176 R0 SYMATTR InstName C1 SYMATTR Value 3p SYMBOL cap 496 176 R0 SYMATTR InstName C2 SYMATTR Value 1n SYMBOL cap 128 32 R0 WINDOW 0 49 42 Left 0 WINDOW 3 50 73 Left 0 SYMATTR InstName C3 SYMATTR Value 47p SYMBOL Opamps\\LT1492 32 -32 R0 WINDOW 0 -76 -33 Left 0 WINDOW 3 -104 3 Left 0 SYMATTR InstName U1 SYMBOL res 320 16 R90 WINDOW 0 -45 59 VBottom 0 WINDOW 3 -36 60 VTop 0 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL res 320 128 R90 WINDOW 0 72 52 VBottom 0 WINDOW 3 78 52 VTop 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL nmos 368 -48 R0 SYMATTR InstName M1 SYMATTR Value FDC637AN SYMBOL voltage 608 -128 R0 WINDOW 0 55 39 Left 0 WINDOW 3 53 82 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 1.5 SYMBOL voltage -208 80 R0 WINDOW 3 -161 182 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(1.1 1.15 100u 0 0 200u) SYMATTR InstName V2 SYMBOL voltage 144 -160 R0 WINDOW 0 61 23 Left 0 WINDOW 3 60 60 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 12 SYMBOL res 592 160 R0 WINDOW 0 58 43 Left 0 WINDOW 3 64 76 Left 0 SYMATTR InstName R3 SYMATTR Value .001 SYMBOL res 496 256 R0 WINDOW 0 47 62 Left 0 WINDOW 3 41 98 Left 0 SYMATTR InstName R4 SYMATTR Value 0.05 SYMBOL res 320 176 R0 SYMATTR InstName R5 SYMATTR Value 100 SYMBOL sw 688 400 R180 WINDOW 3 32 -11 Left 0 SYMATTR Value MYSW SYMATTR InstName S1 SYMBOL voltage 848 320 R0 WINDOW 3 -161 182 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 1 500u 10n 10n 200u) SYMATTR InstName V4 TEXT 88 288 Left 0 !.tran 0.0012 TEXT -456 -136 Left 0 ;TEM2 LDO REGULATORS TEXT -416 -88 Left 0 ;JL Sep 12 2011 TEXT 712 288 Left 0 !.model MYSW SW(Ron=1 Roff=1Meg Vt=.5 Vh=-.99)

I my case, +12 is for sure up first, since it's the prime power. So

1.1 and 1.2 will follow the 1.5 volt supply (a soft-start switcher) up, fets saturated, and flatten out when they hit their targets. The likelyhood of something downstream latching up, at these voltages, is about nil.

Some older Xilinx parts had sequencing requirements, but the ewer ones don't seem to. This project is Altera, and I don't think this chup has sequencing requirements. We will check for that.

John

Intelligent? uP based?

Jihn

I'm powering an FPGA and some Pericon equalizer chips, so I have to have a bunch of bypass caps across the output, both for the fast stuff and as bulk energy storage for when the current changes hundreds of mA in nanoseconds, sort of like an Intel CPU sputtering on and off as the compute load changes.

But a faster feedback loop does improve the transient regulation, even though it technically makes the loop look underdamped. I guess peak excursion is what matters, not how ringy the recovery looks.

It does ring hard, and then oscillate, as you reduce the R2-C3 time constant.

Maybe a tantalum across the output would help; their ESR often fixes things.

John

    | |    | |

Some of the Altera parts require that the core voltage (the lowest one) be stable before the others start to ramp up. I have no way of knowing whether that applies to the part you're using.

Regards, Allan

--
~ 25µs to 90% of Eout, according to LTspice.

--
Not really, although there's a little µC in there to do some math.

Arria II GX. Maybe I should find out! I can program the various soft-starts on the many switchers, and specifically have the 0.9 come up first. Thanks.

John

Excellent whining! You do that so well.

John